06 Apr, 2017
1 commit
-
The peripherals' RAS functionality only exist on the Arria10 SoCFPGA.
The Cyclone5 initialization generates EDAC warnings when the peripherals
aren't found in the device tree. Fix by checking for Arria10 in the init
functions.Signed-off-by: Thor Thayer
Cc: linux-edac
Link: http://lkml.kernel.org/r/1491415262-5018-1-git-send-email-thor.thayer@linux.intel.com
Signed-off-by: Borislav Petkov
15 Dec, 2016
1 commit
-
Now, all left at edac_core.h are at drivers/edac/edac_mc.c,
so rename it to edac_mc.h.Signed-off-by: Mauro Carvalho Chehab
23 Oct, 2016
1 commit
-
Disable IRQs while injecting SDRAM errors. The RT patches exposed
a spinlock deadlock where the spinlock taken for the regmap write
deadlocked with the IRQ clear regmap write.Error injection is not normally enabled for ECC but only for testing.
Signed-off-by: Thor Thayer
Cc: linux-edac
Link: http://lkml.kernel.org/r/1476906827-9412-1-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
23 Sep, 2016
2 commits
-
Add the IRQF_ONESHOT and IRQF_TRIGGER_HIGH flags to disable the IRQ
while executing the IRQ handler. Remove the IRQF_SHARED because these
are not shared IRQs in the domain. Exposed when flooding IRQs.Signed-off-by: Thor Thayer
Cc: linux-edac
Link: http://lkml.kernel.org/r/1474582419-7053-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
Correct the error message sent out in the case of a single bit error IRQ
allocation.Signed-off-by: Thor Thayer
Cc: linux-edac
Link: http://lkml.kernel.org/r/1474582419-7053-1-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
01 Sep, 2016
2 commits
-
Rename the Memory Controller debug trigger to the same common name as
the EDAC devices.Signed-off-by: Thor Thayer
Cc: linux-edac
Link: http://lkml.kernel.org/r/1471622666-15197-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
The L2 and OCRAM devices have different ecc trigger names than the other
EDAC devices (FIFO peripherals). Make them all the same and remove the
character array from the device structure.Signed-off-by: Thor Thayer
Cc: linux-edac
Link: http://lkml.kernel.org/r/1471622666-15197-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
11 Aug, 2016
1 commit
-
Fix the following sparse warning:
drivers/edac/altera_edac.c:1649:23: warning:
symbol 'a10_eccmgr_ic_ops' was not declared. Should it be static?Signed-off-by: Wei Yongjun
Reviewed-by: Thor Thayer
Cc: linux-edac
Cc: lkml
Link: http://lkml.kernel.org/r/1470836667-11822-1-git-send-email-weiyj.lk@gmail.com
Signed-off-by: Borislav Petkov
10 Aug, 2016
1 commit
-
Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC is a
dual port RAM implementation which is different than any of the other
peripherals and therefore requires additional code.Signed-off-by: Thor Thayer
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1470753653-23465-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
08 Aug, 2016
4 commits
-
Add Altera Arria10 QSPI FIFO memory support.
Signed-off-by: Thor Thayer
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1468512408-5156-9-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
Add Altera Arria10 USB FIFO memory support.
Signed-off-by: Thor Thayer
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1468512408-5156-8-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
Add Altera Arria10 DMA FIFO memory support.
Signed-off-by: Thor Thayer
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1468512408-5156-7-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
Add Altera Arria10 NAND FIFO memory support.
Signed-off-by: Thor Thayer
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1468512408-5156-6-git-send-email-tthayer@opensource.altera.com
[ Reformat loop in altr_edac_a10_probe() for better readability. ]
Signed-off-by: Borislav Petkov
25 Jun, 2016
2 commits
-
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update to support
a common compatibility string for all Ethernet FIFOs in the DT.Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1466603939-7526-8-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for additional memory module ECCs, add the memory
initialization functions and helpers.Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1466603939-7526-7-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
24 Jun, 2016
4 commits
-
Make the IRQ and check_deps() functions available to all the memory
buffers by moving them outside of the OCRAM only area.Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1466603939-7526-5-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for additional memory module ECCs, the IRQ function will
check a panic flag before doing a kernel panic on double bit errors.OCRAM uncorrectable errors cause a panic because sleep/resume functions
and FPGA contents during sleep are stored in OCRAM.ECCs on peripheral FIFO buffers will not cause a kernel panic on DBERRs
because the packet can be retried and therefore recovered.Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1466603939-7526-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for the Arria10 ECC modules, check the status of the
parent in the device tree to ensure the block is enabled. Skip if no
parent phandle is set in the device tree.Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1466603939-7526-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
The device private data structures are used only here so make them
static.Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1466603939-7526-4-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
08 Jun, 2016
2 commits
-
Separate the device match arrays for each platform to prevent CycloneV
matches when calling of_platform_populate() on the Arria10 ECC manager
node.If the SDRAM is a child node of ECC manager, call probe function via
of_platform_populate().Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1464193783-5071-4-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
To better support child devices, the ECC manager needs to be
implemented as an IRQ controller.Signed-off-by: Thor Thayer
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Link: http://lkml.kernel.org/r/1465331757-10227-1-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
23 Apr, 2016
2 commits
-
The recently added Arria10 OCRAM ECC support caused some new harmless
warnings about unused functions when it is disabled:drivers/edac/altera_edac.c:1067:20: error: 'altr_edac_a10_ecc_irq' defined but not used [-Werror=unused-function]
drivers/edac/altera_edac.c:658:12: error: 'altr_check_ecc_deps' defined but not used [-Werror=unused-function]This rearranges the code slightly to have those two functions inside
of the same #ifdef that hides their callers. It also manages to
avoid a forward declaration of the IRQ handler in the process.Signed-off-by: Arnd Bergmann
Acked-by: Thor Thayer
Cc: Alan Tull
Cc: Dinh Nguyen
Cc: linux-edac
Fixes: c7b4be8db8bc ("EDAC, altera: Add Arria10 OCRAM ECC support")
Link: http://lkml.kernel.org/r/1460837650-1237650-2-git-send-email-arnd@arndb.de
Signed-off-by: Borislav Petkov -
The altera EDAC driver refers to its per-device data
using a cast to '(void *)', which makes the pointer
non-const, though both the source and destination are
actually const.Removing the annotation makes the reference (almost)
fit into a single line for improved readability, and
ensures that it is actually defined as const.Signed-off-by: Arnd Bergmann
Acked-by: Thor Thayer
Cc: Alan Tull
Cc: Dinh Nguyen
Cc: linux-edac
Link: http://lkml.kernel.org/r/1460837650-1237650-1-git-send-email-arnd@arndb.de
Signed-off-by: Borislav Petkov
07 Apr, 2016
1 commit
-
Add Arria10 On-Chip RAM ECC handling.
Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1459992174-8015-1-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
02 Apr, 2016
3 commits
-
In preparation for the Arria10 peripheral ECCs, move the OCRAM ECC
dependency check into the general ECC area since this same function can
be used by other memories.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1459450087-24792-4-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for the Arria10 peripheral ECCs, add a register offset
from the ECC base to index to the ECC enable register.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1459450087-24792-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for the Arria10 peripheral ECCs, extract the inject file
operations because the Arria10 IRQ trigger mechanism is different than
Cyclone5/Arria5 and Arria10 L2 cache.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1459450087-24792-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
29 Mar, 2016
5 commits
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Add a private data structure for Arria10 L2 cache ECC and the probe
function for it.The Arria10 ECC device IRQs are in a shared register so the ECC Manager
parent/child relationship requires a different probe function.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1458576106-24505-8-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for the Arria10 peripheral ECCs, add a register offset
from the ECC base to the private data structure to index to the error
injection register.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1458576106-24505-6-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for the Arria10 peripheral ECCs, use the ECC Enable mask
in place of hard coded masks in the check dependency functions.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1458576106-24505-5-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
In preparation for the Arria10 peripheral ECCs, remove the platform
device parameter from the check_deps() functions because it is not
needed and makes the Arria10 check_deps() cleaner.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1458576106-24505-4-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
Move the device structs and defines to altera_edac.h in preparation for
adding the Arria10 L2 cache ECC.Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac
Link: http://lkml.kernel.org/r/1458576106-24505-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
11 Feb, 2016
1 commit
-
Add L2 Cache and On-Chip RAM EDAC support for the Altera SoCs. The SDRAM
controller is using the Memory Controller model.Each type of ECC is individually configurable.
Signed-off-by: Thor Thayer
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac
Cc: mark.rutland@arm.com
Cc: Mauro Carvalho Chehab
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Link: http://lkml.kernel.org/r/1455132384-17108-1-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
23 Sep, 2015
1 commit
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Use the EDAC-specific wrappers. Drop CONFIG_EDAC_DEBUG ifdeffery.
Cc: Thor Thayer
Cc:
Signed-off-by: Borislav Petkov
25 Jun, 2015
4 commits
-
Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If
EDAC is enabled, it will prevent the platform from going into suspend.The reason is that the IRQ vectors for OCRAM reside on DDR and in
Suspend-to-RAM mode we're executing out of OCRAM. If an ECC error
occurs, we can't handle it so it was decided to make them mutually
exclusive.Signed-off-by: Alan Tull
Signed-off-by: Dinh Nguyen
Cc: dinh.linux@gmail.com
Cc: dougthompson@xmission.com
Cc: linux-edac
Cc: mchehab@osg.samsung.com
Cc: tthayer@opensource.altera.com
Link: http://lkml.kernel.org/r/1433512155-9906-1-git-send-email-dinguyen@opensource.altera.com
Signed-off-by: Borislav Petkov -
The Arria10 SDRAM and ECC system differs significantly from the
Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10
SoC.
1) IRQ handler needs to support SHARED IRQ
2) Support sberr and dberr address reporting.Signed-off-by: Thor Thayer
Cc: Arnd Bergmann
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Cc: m.chehab@samsung.com
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: tthayer.linux@gmail.com
Link: http://lkml.kernel.org/r/1433428128-7292-4-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
The Arria10 SoC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.Signed-off-by: Thor Thayer
Cc: Arnd Bergmann
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Cc: m.chehab@samsung.com
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: tthayer.linux@gmail.com
Link: http://lkml.kernel.org/r/1433428128-7292-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov -
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. The memory size is calculated in the
bootloader and passed via the device tree. Using this device tree size
is more generic than using the register fields to calculate the memory
size for different SDRAM controllers.Signed-off-by: Thor Thayer
Cc: Arnd Bergmann
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac
Cc: m.chehab@samsung.com
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: tthayer.linux@gmail.com
Link: http://lkml.kernel.org/r/1433428128-7292-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov
05 Sep, 2014
1 commit
-
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1][1] https://lkml.org/lkml/2014/7/30/514
[dinguyen] Fixed Kconfig to have EDAC_ALTERA_MC as a tristate to prevent a
build failure for allmodconfig.Signed-off-by: Thor Thayer
Acked-by: Borislav Petkov
[dinguyen] cleaned up commit message
Signed-off-by: Dinh Nguyen