Eric Lee / smarc-fsl-linux-kernel

01 Sep, 2016

1 commit

  • f399f34bd   EDAC, altera: Rename device trigger to common name ... Browse Code »

    The L2 and OCRAM devices have different ecc trigger names than the other
    EDAC devices (FIFO peripherals). Make them all the same and remove the
    character array from the device structure.

    Signed-off-by: Thor Thayer
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1471622666-15197-2-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

10 Aug, 2016

1 commit

  • 911049845   EDAC, altera: Add Arria10 SD-MMC EDAC support ... Browse Code »

    Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC is a
    dual port RAM implementation which is different than any of the other
    peripherals and therefore requires additional code.

    Signed-off-by: Thor Thayer
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1470753653-23465-3-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

25 Jun, 2016

2 commits

  • ab8c1e0fb   EDAC, altera: Add Arria10 Ethernet EDAC support ... Browse Code »

    Add Altera Arria10 Ethernet FIFO memory EDAC support. Update to support
    a common compatibility string for all Ethernet FIFOs in the DT.

    Signed-off-by: Thor Thayer
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1466603939-7526-8-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     
  • 1166fde93   EDAC, altera: Add Arria10 ECC memory init functions ... Browse Code »

    In preparation for additional memory module ECCs, add the memory
    initialization functions and helpers.

    Signed-off-by: Thor Thayer
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1466603939-7526-7-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

24 Jun, 2016

1 commit

  • 2b083d65f   EDAC, altera: Add panic flag check to A10 IRQ ... Browse Code »

    In preparation for additional memory module ECCs, the IRQ function will
    check a panic flag before doing a kernel panic on double bit errors.

    OCRAM uncorrectable errors cause a panic because sleep/resume functions
    and FPGA contents during sleep are stored in OCRAM.

    ECCs on peripheral FIFO buffers will not cause a kernel panic on DBERRs
    because the packet can be retried and therefore recovered.

    Signed-off-by: Thor Thayer
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1466603939-7526-3-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

08 Jun, 2016

1 commit

  • 13ab8448d   EDAC, altera: Add ECC Manager IRQ controller support ... Browse Code »

    To better support child devices, the ECC manager needs to be
    implemented as an IRQ controller.

    Signed-off-by: Thor Thayer
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1465331757-10227-1-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

07 Apr, 2016

1 commit

  • c7b4be8db   EDAC, altera: Add Arria10 OCRAM ECC support ... Browse Code »

    Add Arria10 On-Chip RAM ECC handling.

    Signed-off-by: Thor Thayer
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux@arm.linux.org.uk
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1459992174-8015-1-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

02 Apr, 2016

2 commits

  • 943ad9179   EDAC, altera: Add register offset for ECC Enable ... Browse Code »

    In preparation for the Arria10 peripheral ECCs, add a register offset
    from the ECC base to index to the ECC enable register.

    Signed-off-by: Thor Thayer
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux@arm.linux.org.uk
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1459450087-24792-3-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     
  • e17ced2cb   EDAC, altera: Extract error inject operations to a struct fops ... Browse Code »

    In preparation for the Arria10 peripheral ECCs, extract the inject file
    operations because the Arria10 IRQ trigger mechanism is different than
    Cyclone5/Arria5 and Arria10 L2 cache.

    Signed-off-by: Thor Thayer
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux@arm.linux.org.uk
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1459450087-24792-2-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

29 Mar, 2016

4 commits

  • 588cb03ea   EDAC, altera: Add Arria10 L2 Cache ECC handling ... Browse Code »

    Add a private data structure for Arria10 L2 cache ECC and the probe
    function for it.

    The Arria10 ECC device IRQs are in a shared register so the ECC Manager
    parent/child relationship requires a different probe function.

    Signed-off-by: Thor Thayer
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux@arm.linux.org.uk
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1458576106-24505-8-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     
  • 811fce4f2   EDAC, altera: Add register offset for ECC Error Inject ... Browse Code »

    In preparation for the Arria10 peripheral ECCs, add a register offset
    from the ECC base to the private data structure to index to the error
    injection register.

    Signed-off-by: Thor Thayer
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux@arm.linux.org.uk
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1458576106-24505-6-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     
  • 328ca7ae8   EDAC, altera: Remove platform device from check_deps() ... Browse Code »

    In preparation for the Arria10 peripheral ECCs, remove the platform
    device parameter from the check_deps() functions because it is not
    needed and makes the Arria10 check_deps() cleaner.

    Signed-off-by: Thor Thayer
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux@arm.linux.org.uk
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1458576106-24505-4-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     
  • 05b088b6f   EDAC, altera: Move device structs and defines to the header ... Browse Code »

    Move the device structs and defines to altera_edac.h in preparation for
    adding the Arria10 L2 cache ECC.

    Signed-off-by: Thor Thayer
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux@arm.linux.org.uk
    Cc: linux-edac
    Link: http://lkml.kernel.org/r/1458576106-24505-3-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     

15 Oct, 2015

1 commit

  • 941fd2e70   EDAC, altera: SoCFPGA EDAC should not look for ECC_CORR_EN ... Browse Code »

    The bootloader may or may not enable the ECC_CORR_EN bit. By
    not enabling ECC_CORR_EN, when error happens, it is the user's
    responsibility to perform a full SDRAM scrub.

    Remove the check for ECC_CORR_EN.

    Signed-off-by: Dinh Nguyen
    Cc: linux-edac
    Cc: Mauro Carvalho Chehab
    Cc: Thor Thayer
    Link: http://lkml.kernel.org/r/1444864456-21778-1-git-send-email-dinguyen@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Dinh Nguyen
     

23 Sep, 2015

1 commit

25 Jun, 2015

2 commits

  • 73bcc942f   EDAC, altera: Add Arria10 EDAC support ... Browse Code »

    The Arria10 SDRAM and ECC system differs significantly from the
    Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10
    SoC.
    1) IRQ handler needs to support SHARED IRQ
    2) Support sberr and dberr address reporting.

    Signed-off-by: Thor Thayer
    Cc: Arnd Bergmann
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: galak@codeaurora.org
    Cc: grant.likely@linaro.org
    Cc: ijc+devicetree@hellion.org.uk
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-edac
    Cc: m.chehab@samsung.com
    Cc: mark.rutland@arm.com
    Cc: pawel.moll@arm.com
    Cc: robh+dt@kernel.org
    Cc: tthayer.linux@gmail.com
    Link: http://lkml.kernel.org/r/1433428128-7292-4-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer
     
  • 143f4a5ac   EDAC, altera: Refactor for Altera CycloneV SoC ... Browse Code »

    The Arria10 SoC uses a completely different SDRAM controller from the
    earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
    for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.

    Signed-off-by: Thor Thayer
    Cc: Arnd Bergmann
    Cc: devicetree@vger.kernel.org
    Cc: dinguyen@opensource.altera.com
    Cc: galak@codeaurora.org
    Cc: grant.likely@linaro.org
    Cc: ijc+devicetree@hellion.org.uk
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-edac
    Cc: m.chehab@samsung.com
    Cc: mark.rutland@arm.com
    Cc: pawel.moll@arm.com
    Cc: robh+dt@kernel.org
    Cc: tthayer.linux@gmail.com
    Link: http://lkml.kernel.org/r/1433428128-7292-3-git-send-email-tthayer@opensource.altera.com
    Signed-off-by: Borislav Petkov

    Thor Thayer