10 Mar, 2017
1 commit
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Fix typos and add the following to the scripts/spelling.txt:
disble||disable
disbled||disabledI kept the TSL2563_INT_DISBLED in /drivers/iio/light/tsl2563.c
untouched. The macro is not referenced at all, but this commit is
touching only comment blocks just in case.Link: http://lkml.kernel.org/r/1481573103-11329-20-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
11 Feb, 2017
2 commits
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There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.Signed-off-by: Wei Yongjun
Reviewed-by: Marek Vasut
Signed-off-by: Brian Norris -
From Cyrille:
"""
This pull request contains the following notable changes:
- add support to the 4-byte address instruction set.
- add support to new memory parts.
- add support to S3AN memories.
- add support to the Intel SPI controller.
- add support to the Aspeed AST2400 and AST2550 controllers.
- fix max SPI transfer and message sizes in m25p80_read().
- fix the Candence QSPI driver.
- fix the Freescale QSPI driver.
"""
10 Feb, 2017
15 commits
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Checking for ret < 0 is redundant because a previous check on ret
being non-zero already handles the ret < 0 case. Remove the redundant
code. Found by CoverityScan, CID#1398863, CID#1398864Signed-off-by: Colin Ian King
Reviewed-by: Richard Weinberger
Acked-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
Acked-by: Han xu
Signed-off-by: Cyrille Pitchen -
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
Acked-by: Han xu
Signed-off-by: Cyrille Pitchen -
Add GigaDevice GD25Q16 (16M-bit) to supported list.
Signed-off-by: Kamal Dasu
Acked-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
The page calculation under spi_nor_s3an_addr_convert() was wrong. On
Default Address Mode we need to perform a divide by page_size.Signed-off-by: Ricardo Ribalda Delgado
Acked-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
The first argument of ioread32_rep() and ioread8_rep is not
const. Change aspeed_smc_read_from_ahb() prototype to fix compile
warning :drivers/mtd/spi-nor/aspeed-smc.c: In function 'aspeed_smc_read_from_ahb':
drivers/mtd/spi-nor/aspeed-smc.c:212:16: warning: passing argument 1 of 'ioread32_rep' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
ioread32_rep(src, buf, len >> 2);Signed-off-by: Cédric Le Goater
Reviewed-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
From Lee Jones:
"""
Immutable branch between MFD and MTD due for the v4.11 merge window
""" -
This chip has write protection enabled on power-up,
so this flag is necessary to support write operations.Signed-off-by: Victor Shyba
Acked-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
This patch provides an alternative mean to support memory above 16MiB
(128Mib) by replacing 3byte address op codes by their associated 4byte
address versions.Using the dedicated 4byte address op codes doesn't change the internal
state of the SPI NOR memory as opposed to using other means such as
updating a Base Address Register (BAR) and sending command to enter/leave
the 4byte mode.Hence when a CPU reset occurs, early bootloaders don't need to be aware
of BAR value or 4byte mode being enabled: they can still access the first
16MiB of the SPI NOR memory using the regular 3byte address op codes.Signed-off-by: Cyrille Pitchen
Tested-by: Vignesh R
Acked-by: Marek Vasut -
This patch renames the SPINOR_OP_* macros of the 4-byte address
instruction set so the new names all share a common pattern: the 4-byte
address name is built from the 3-byte address name appending the "_4B"
suffix.The patch also introduces new op codes to support other SPI protocols such
as SPI 1-4-4 and SPI 1-2-2.This is a transitional patch and will help a later patch of spi-nor.c
to automate the translation from the 3-byte address op codes into their
4-byte address version.Signed-off-by: Cyrille Pitchen
Acked-by: Mark Brown
Acked-by: Marek Vasut -
This driver adds mtd support for the Aspeed AST2400 SoC static memory
controllers:* New Static Memory Controller (referred as FMC)
. BMC firmware
. AST2500 compatible register set
. 5 chip select pins (CE0 ∼ CE4)
. supports NOR flash, NAND flash and SPI flash memory.* SPI Flash Controller (SPI)
. host Firmware
. slightly different register set, between AST2500 and the legacy
controller
. supports SPI flash memory
. 1 chip select pin (CE0)The legacy static memory controller (referred as SMC) is not
supported, as well as types other than SPI.Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Signed-off-by: Cyrille Pitchen -
This driver adds mtd support for the Aspeed AST2500 SoC static memory
controllers :* Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. supports SPI type flash memory (CE0-CE1)
. CE2 can be of NOR type flash but this is not supported by the
driver* SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. supports SPI type flash memoryEach controller has a memory range on which it maps its flash module
slaves. Each slave is assigned a memory window for its mapping that
can be changed at bootime with the Segment Address Register.Each SPI flash slave can then be accessed in two modes: Command and
User. When in User mode, accesses to the memory segment of the slaves
are translated in SPI transfers. When in Command mode, the HW
generates the SPI commands automatically and the memory segment is
accessed as if doing a MMIO.Currently, only the User mode is supported. Command mode needs a
little more work to check that the memory window on the AHB bus fits
the module size.Based on previous work from Milton D. Miller II
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
This patch removes the WARN_ONCE() test in spi_nor_write().
This macro triggers the display of a warning message almost every time we
use a UBI file-system because a write operation is performed at offset 64,
which is in the middle of the SPI NOR memory page. This is a valid
operation for ubifs.Hence this warning is pretty annoying and useless so we just remove it.
Signed-off-by: Cyrille Pitchen
Suggested-by: Richard Weinberger
Suggested-by: Andras Szemzo
Acked-by: Boris Brezillon -
The patch checks whether the Quad Enable bit is already set in the Status
Register. If so, the function exits immediately with a successful return
code.Signed-off-by: Cyrille Pitchen
Reviewed-by: Jagan Teki
Acked-by: Marek Vasut -
Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep
their configuration data and (optionally) some user data.The protocol of this flash follows most of the spi-nor standard. With
the following differences:- Page size might not be a power of two.
- The address calculation (default addressing mode).
- The spi nor commands used.Protocol is described on Xilinx User Guide UG333
Signed-off-by: Ricardo Ribalda Delgado
Cc: Boris Brezillon
Cc: Brian Norris
Cc: Marek Vasut
Reviewed-by: Marek Vasut
Signed-off-by: Cyrille Pitchen
09 Feb, 2017
1 commit
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Trivial typo fix in comment.
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Brian Norris
04 Jan, 2017
2 commits
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The x86-64 and some other architectures are missing readsl/writesl
functions, so this driver won't build on them. Use a more portable
ioread32_rep()/iowrite32_rep() instead.Signed-off-by: Marek Vasut
Cc: Alan Tull
Cc: Brian Norris
Cc: David Woodhouse
Cc: Dinh Nguyen
Cc: Graham Moore
Cc: Vignesh R
Cc: Yves Vandervennet
Suggested-by: Stefan Roese
Signed-off-by: Cyrille Pitchen -
Add support for the SPI serial flash host controller found on many Intel
CPUs including Baytrail and Braswell. The SPI serial flash controller is
used to access BIOS and other platform specific information. By default the
driver exposes a single read-only MTD device but with a module parameter
"writeable=1" the MTD device can be made read-write which makes it possible
to upgrade BIOS directly from Linux.Signed-off-by: Mika Westerberg
Acked-by: Cyrille Pitchen
Signed-off-by: Lee Jones
27 Nov, 2016
4 commits
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All fsl_qspi_devtype_data structures are never modified.
This patch constify them.Signed-off-by: LABBE Corentin
Acked-by: Han Xu
Signed-off-by: Cyrille Pitchen -
Add Everspin mr25h40 512KB MRAM to the list of supported chips.
Signed-off-by: Masahiko Iwamoto
Reviewed-by: Jagan Teki
Acked-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.Cc: David Woodhouse
Cc: Brian Norris
Cc: Jagan TekiSigned-off-by: Moritz Fischer
Reviewed-by: Jagan Teki
Signed-off-by: Cyrille Pitchen -
Add Atmel at25df321 spi-nor flash to the list of spi_nor_ids.
Cc: Brian Norris
Cc: Wenyou Yang
Signed-off-by: Jagan Teki
Acked-by: Wenyou Yang
Signed-off-by: Cyrille Pitchen
26 Nov, 2016
4 commits
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We return success or possibly uninitialized values on these error paths
instead of proper error codes.Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: Dan Carpenter
Reviewed-by: Marek Vasut
Reviewed-by: Moritz Fischer
Signed-off-by: Cyrille Pitchen -
There are CQSPI_MAX_CHIPSELECT elements in the ->f_pdata array so the >
should be >=.Fixes: 140623410536 ('mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller')
Signed-off-by: Dan Carpenter
Reviewed-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
Signed-off-by: Sean Nyekjaer
Reviewed-by: Jagan Teki
Acked-by: Marek Vasut
Signed-off-by: Cyrille Pitchen -
The Spansion S25FL128S also supports dual read mode.
In addition remove flag SECT_4K. 4K erases are supported,
but not uniformly.Signed-off-by: Heiner Kallweit
Reviewed-by: Jagan Teki
Acked-by: Marek Vasut
Signed-off-by: Cyrille Pitchen
23 Nov, 2016
2 commits
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With the S25FL127S nor flash part, each writing to the configuration
register takes hundreds of ms. During that time, no more accesses to
the flash should be done (even reads).This commit adds a wait loop after the register writing until the flash
finishes its work.This issue could make rootfs mounting fail when the latter was done too
much closely to this quad enable bit setting step. And in this case, a
driver as UBIFS may try to recover the filesystem and may broke it
completely.Signed-off-by: Joël Esponde
Signed-off-by: Cyrille Pitchen -
Signed-off-by: Ash Benz
Signed-off-by: Cyrille Pitchen
20 Jul, 2016
2 commits
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This controller driver is used only on ARM but is mostly written
portably so it can build on other arch'es. Unfortunately, at least x86
doesn't provibe readsl()/writesl() accessors. We could possibly fix this
issue in the future by using io{read,write}32_rep() instead, but let's
just drop the architectures we aren't using for now.Signed-off-by: Brian Norris
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Remove duplicated include.
Signed-off-by: Wei Yongjun
Signed-off-by: Brian Norris
19 Jul, 2016
1 commit
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Add support for the Cadence QSPI controller. This controller is
present in the Altera SoCFPGA SoCs and this driver has been tested
on the Cyclone V SoC.Signed-off-by: Graham Moore
Signed-off-by: Marek Vasut
Cc: Alan Tull
Cc: Brian Norris
Cc: David Woodhouse
Cc: Dinh Nguyen
Cc: Graham Moore
Cc: Vignesh R
Cc: Yves Vandervennet
Cc: devicetree@vger.kernel.org
Signed-off-by: Brian Norris
16 Jul, 2016
1 commit
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This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
controller.Signed-off-by: Cyrille Pitchen
Acked-by: Nicolas Ferre
Signed-off-by: Brian Norris
14 Jul, 2016
3 commits
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Add hisilicon spi-nor flash controller driver
Signed-off-by: Binquan Peng
Signed-off-by: Jiancheng Xue
Acked-by: Rob Herring
Reviewed-by: Ezequiel Garcia
Reviewed-by: Jagan Teki
Reviewed-by: Cyrille Pitchen
Signed-off-by: Brian Norris -
Gigadevice flash support BP{0,1,2,3,4} bits, where BP3 means the same as
the existing supported TB (Top/Bottom), and BP4 means the same as the
not-yet-supported 4K bit used on other flash (e.g., Winbond). Let's
support lock/unlock with the same feature flags as w25q32dw/w25q64dw.Tested on gd25lq64c, but I checked datasheets for the other 3, to make
sure.While I was at it, I noticed that these all support dual and quad as
well. I noted them, but can't test them at the moment, since my test
system only supports standard 1x SPI.Signed-off-by: Brian Norris
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Add Micron (n25q00a) 1Gbit NOR Flash in the list of supported
devices.
This part is different from n25q00 in Memory Type.
Memory Type for n25q00 - BAh
Memory Type for n25q00a - BBhSigned-off-by: P L Sai Krishna
Signed-off-by: Brian Norris
10 Jul, 2016
1 commit
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In stm_unlock(), the test to determine whether we've fully unlocked the
flash checks for the lock length to be equal to the flash size. That is
a typo/think-o -- the condition actually means the flash is completely
*locked.* We should be using the inverse condition -- that the lock
length is 0 (i.e., no protection).The result of this bug is that we never actually turn off the Status
Register Write Disable bit, even if the flash is completely unlocked.
Now we can.Fixes: 47b8edbf0d43 ("mtd: spi-nor: disallow further writes to SR if WP# is low")
Reported-by: Giorgio
Signed-off-by: Brian Norris
Cc: Ezequiel Garcia
02 Jun, 2016
1 commit
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mtdblock and ubi do not handle the situation when read returns less data
than requested. Loop in spi-nor until buffer is filled or an error is
returned.Signed-off-by: Michal Suchanek
Signed-off-by: Brian Norris
Tested-by Cyrille Pitchen
Acked-by: Michal Suchanek
Tested-by: Michal Suchanek
