06 Dec, 2011
2 commits
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Allows devices to discover their own interrupt without having to remember
it themselves.Signed-off-by: Mark Brown
05 Dec, 2011
2 commits
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…nie/regmap into regmap-next
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Sometimes the register map information may change in ways that drivers can
discover at runtime. For example, new revisions of a device may add new
registers. Support runtime discovery by drivers by allowing the register
cache to be reinitialised with a new function regmap_reinit_cache() which
discards the existing cache and creates a new one.Signed-off-by: Mark Brown
30 Nov, 2011
1 commit
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Some users of regmap_update_bits() would like to be able to tell their
users if they actually did an update so provide a variant which also
returns a flag indicating if an update took place. We could return a
tristate in the return value of regmap_update_bits() but this makes the
API more cumbersome to use and doesn't fit with the general zero for
success idiom we have.Signed-off-by: Mark Brown
21 Nov, 2011
1 commit
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There should be no situation where it offers any advantage over rbtree
and there are no current users so remove the code for simplicity.Signed-off-by: Mark Brown
17 Nov, 2011
1 commit
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The reg_defaults field usually points to a static per driver array, which should
not be modified. Make requirement this explicit by making reg_defaults const.
To allow this the regcache_init code needs some minor changes. Previoulsy the
reg_config was not available in regcache_init and regmap->reg_defaults was used
to pass the default register set to regcache_init. Now that the reg_config is
available we can work on it directly.Signed-off-by: Lars-Peter Clausen
Signed-off-by: Mark Brown
08 Nov, 2011
4 commits
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Users probably don't care about the specific compression algorithm and
we might want to use a different algorithm (snappy being the one I'm
thinking of right now) so update the public interface to have a more
generic name.Signed-off-by: Mark Brown
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Allow drivers to optimise out the register cache sync if they didn't need
to do one. If the hardware is desynced from the register cache (by power
loss for example) then the driver should call regcache_mark_dirty() to
let the core know about this.Signed-off-by: Mark Brown
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There seem to be lots of regmap-using devices with very similar interrupt
controllers with a small bank of interrupt registers and mask registers
with an interrupt per bit. This won't cover everything but it's a good
start.Each chip supplies a base for the status registers, a base for the mask
registers, an optional base for writing acknowledgements (which may be the
same as the status registers) and an array of bits within each of these
register banks which indicate the interrupt.There is an assumption that the bit for each interrupt will be the same
in each of the register bank.Signed-off-by: Mark Brown
01 Nov, 2011
1 commit
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The pretty much brings in the kitchen sink along
with it, so it should be avoided wherever reasonably possible in
terms of being included from other commonly used
files, as it results in a measureable increase on compile times.The worst culprit was probably device.h since it is used everywhere.
This file also had an implicit dependency/usage of mutex.h which was
masked by module.h, and is also fixed here at the same time.There are over a dozen other headers that simply declare the
struct instead of pulling in the whole file, so follow their lead
and simply make it a few more.Most of the implicit dependencies on module.h being present by
these headers pulling it in have been now weeded out, so we can
finally make this change with hopefully minimal breakage.Signed-off-by: Paul Gortmaker
30 Sep, 2011
1 commit
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Ensure we've got a function so users can enable/disable the
cache bypass option.Signed-off-by: Dimitris Papastamos
Signed-off-by: Mark Brown
20 Sep, 2011
6 commits
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Signed-off-by: Mark Brown
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Signed-off-by: Mark Brown
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This patch adds support for LZO compression when storing the register
cache.For a typical device whose register map would normally occupy 25kB or 50kB
by using the LZO compression technique, one can get down to ~5-7kB. There
might be a performance penalty associated with each individual read/write
due to decompressing/compressing the underlying cache, however that should not
be noticeable. These memory benefits depend on whether the target architecture
can get rid of the memory occupied by the original register defaults cache
which is marked as __devinitconst. Nevertheless there will be some memory
gain even if the target architecture can't get rid of the original register
map, this should be around ~30-32kB instead of 50kB.Signed-off-by: Dimitris Papastamos
Signed-off-by: Mark Brown -
This patch adds support for the rbtree cache compression type.
Each rbnode manages a variable length block of registers. There can be no
two nodes with overlapping blocks. Each block has a base register and a
currently top register, all the other registers, if any, lie in between these
two and in ascending order.The reasoning behind the construction of this rbtree is simple. In the
snd_soc_rbtree_cache_init() function, we iterate over the register defaults
provided by the regcache core. For each register value that is non-zero we
insert it in the rbtree. In order to determine in which rbnode we need
to add the register, we first look if there is another register already
added that is adjacent to the one we are about to add. If that is the case
we append it in that rbnode block, otherwise we create a new rbnode
with a single register in its block and add it to the tree.There are various optimizations across the implementation to speed up lookups
by caching the most recently used rbnode.Signed-off-by: Dimitris Papastamos
Tested-by: Lars-Peter Clausen
Signed-off-by: Mark Brown -
This is the simplest form of a cache available in regcache. Any
registers whose default value is 0 are ignored. If any of those
registers are modified in the future, they will be placed in the
cache on demand. The cache layout is essentially using the provided
register defaults by the regcache core directly and does not re-map
it to another representation.Signed-off-by: Dimitris Papastamos
Signed-off-by: Mark Brown -
This patch introduces caching support for regmap. The regcache API
has evolved essentially out of ASoC soc-cache so most of the actual
caching types (except LZO) have been tested in the past.The purpose of regcache is to optimize in time and space the handling
of register caches. Time optimization is achieved by not having to go
over a slow bus like I2C to read the value of a register, instead it is
cached locally in memory and can be retrieved faster. Regarding space
optimization, some of the cache types are better at packing the caches,
for e.g. the rbtree and the LZO caches. By doing this the sacrifice in
time still wins over doing I2C transactions.Signed-off-by: Dimitris Papastamos
Tested-by: Lars-Peter Clausen
Signed-off-by: Mark Brown
06 Sep, 2011
2 commits
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Some buses like SPI have no standard notation of read or write operations.
The general scheme here is to set or clear specific bits in the register
address to indicate whether the operation is a read or write. We already
support having a read flag mask per bus, but as there is no standard
the bits which need to be set or cleared differ between devices and vendors,
thus we need a mechanism to specify them per device.This patch adds two new entries to the regmap_config struct, read_flag_mask and
write_flag_mask. These will be or'ed onto the top byte when doing a read or
write operation. If both masks are empty the device will fallback to the
regmap_bus masks.Signed-off-by: Lars-Peter Clausen
Signed-off-by: Mark Brown -
No longer used as users link directly with the bus types so the core
module infrastructure does refcounting for us.Signed-off-by: Mark Brown
21 Aug, 2011
2 commits
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It is useful for the register cache code to be able to specify the
default values for the device registers. The major use is when restoring
the register cache after suspend, knowing the register defaults allows
us to skip registers that are at their default values when we resume which
can be a substantial win on larger modern devices. For some devices
(mostly older ones) the hardware does not support readback so the only way we
can know the values is from code and so initializing the cache with default
values makes it much easier for drivers work with read/modify/write
updates.Signed-off-by: Mark Brown
09 Aug, 2011
2 commits
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We no longer enumerate the bus types, we rely on the driver telling us
this on init.Signed-off-by: Mark Brown
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Field names didn't match between the documentation and the code.
Signed-off-by: Mark Brown
08 Aug, 2011
3 commits
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Some devices are sensitive to reads on their registers, especially for
things like clear on read interrupt status registers. Avoid creating
problems with these with things like debugfs by allowing drivers to tell
the core about them. If a register is marked as precious then the core
will not internally generate any reads of it.Signed-off-by: Mark Brown
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This is currently unused but we need to know which registers exist and
their properties in order to implement diagnostics like register map
dumps and the cache features.We use callbacks partly because properties can vary at runtime (eg, through
access locks on registers) and partly because big switch statements are a
good compromise between readable code and small data size for providing
information on big register maps.Signed-off-by: Mark Brown
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Signed-off-by: Mark Brown
23 Jul, 2011
3 commits
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Signed-off-by: Mark Brown
Acked-by: Liam Girdwood
Acked-by: Wolfram Sang
Acked-by: Grant Likely -
Signed-off-by: Mark Brown
Acked-by: Liam Girdwood
Acked-by: Wolfram Sang
Acked-by: Grant Likely -
There are many places in the tree where we implement register access for
devices on non-memory mapped buses, especially I2C and SPI. Since hardware
designers seem to have settled on a relatively consistent set of register
interfaces this can be effectively factored out into shared code. There
are a standard set of formats for marshalling data for exchange with the
device, with the actual I/O mechanisms generally being simple byte
streams.We create an abstraction for marshaling data into formats which can be
sent on the control interfaces, and create a standard method for
plugging in actual transport underneath that.This is mostly a refactoring and renaming of the bottom level of the
existing code for sharing register I/O which we have in ASoC. A
subsequent patch in this series converts ASoC to use this. The main
difference in interface is that reads return values by writing to a
location provided by a pointer rather than in the return value, ensuring
we can use the full range of the type for register data. We also use
unsigned types rather than ints for the same reason.As some of the devices can have very large register maps the existing
ASoC code also contains infrastructure for managing register caches.
This cache work will be moved over in a future stage to allow for
separate review, the current patch only deals with the physical I/O.Signed-off-by: Mark Brown
Acked-by: Liam Girdwood
Acked-by: Greg Kroah-Hartman
Acked-by: Wolfram Sang
Acked-by: Grant Likely