25 Aug, 2020
1 commit
16 Apr, 2020
1 commit
12 Oct, 2019
5 commits
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Enable all SECO MUs and increase number of users on the first one.
Signed-off-by: Stéphane Dion
(cherry picked from commit 56099536022e7e66cfc932069aa4a4701d84aa0b) -
enable all SECO MUs and increase number of users on the first one.
Signed-off-by: Stéphane Dion
(cherry picked from commit 2197e1f3a75fe9d9832cff3aa979aa4235a1e7a7) -
Enabling use of the first SECO MU on i.MX8QM
Signed-off-by: Stephane Dion
(cherry picked from commit 2b65b323254965b1d563e0aee80e18678d631b9d) -
Enabling use of the first SECO MU on i.MX8QXP
Signed-off-by: Stephane Dion
(cherry picked from commit b7865b23439de010187a211d1c283d6159807569) -
Driver to communicate with SECO over messaging unit.
Expose a char device to user-space so user can write messages that
will be sent to SECO and read messages received from it.
Data that should be exchanged with SECO through shared memory are
indicated to this driver through ioctl calls.Signed-off-by: Stephane Dion
(cherry picked from commit eb721810fdc309b6a32a7a64c7686eaa6052cdc7)
30 Aug, 2019
1 commit
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The mem clock is used to access the register, if there is no
mem clock defined, we should use the ipg clock instead,
otherwise there will be kernel dump after system reboot.[ 3.010962] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 3.010964] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.19.35-05057-g2134d856e6b2 #2889
[ 3.010966] Hardware name: Freescale i.MX8QXP MEK (DT)
[ 3.010968] Call trace:
[ 3.010969] dump_backtrace+0x0/0x178
[ 3.010971] show_stack+0x14/0x20
[ 3.010972] dump_stack+0x8c/0xac
[ 3.010974] panic+0x120/0x28c
[ 3.010975] __stack_chk_fail+0x0/0x18
[ 3.010977] arm64_serror_panic+0x74/0x80
[ 3.010979] do_serror+0x68/0x130
[ 3.010980] el1_error+0x7c/0xdc
[ 3.010982] _raw_spin_unlock_irqrestore+0xc/0x48
[ 3.010984] clk_core_disable_lock+0x28/0x38
[ 3.010985] clk_disable+0x1c/0x30
[ 3.010987] regmap_mmio_write+0x54/0x68
[ 3.010989] _regmap_bus_reg_write+0x14/0x20
[ 3.010990] _regmap_write+0x60/0xa8
[ 3.010992] regmap_write+0x48/0x70
[ 3.010994] fsl_asrc_probe+0x258/0x660
[ 3.010995] platform_drv_probe+0x50/0xb0Why this issue only happen at kernel reboot, it is because the ipg
clock is enabled in default after system reset, after used once, the
ipg clock is disabled, then reboot system, the issue happen.Signed-off-by: Shengjiu Wang
28 Aug, 2019
2 commits
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On imx8mm gpu AXI should be 800m and AHB 400m but assigned-clock-rates
incorrectly assigned 400m to AXI and left AHB at 800m.Fixes: e744bde4148b ("MLK-21700-4 arm64: dts: imx8mm: Consolidate composite assigned-clocks")
Signed-off-by: Leonard Crestez
Reviewed-by: Abel Vesa -
On 8MQ, it seems that the panel has issues when video-mode used is with
SYNC_EVENTS (default). So, use the video-mode to (SYNC_PULSE), since
the video signal is much stable with this mode.Signed-off-by: Robert Chiras
22 Aug, 2019
1 commit
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Due to the hardware limitation, the power supply for the PADs could not
be off during VLLS mode. To reduce the power consumption under VLLS
state, put all the PADs on iomuxc1 into OFF state before the
system enters into VLLS mode.Signed-off-by: Shenwei Wang
Reviewed-by: Jacky Bai
21 Aug, 2019
1 commit
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Add card detect and write protect support for the sd slot on imx8dxl-phantom-mek
board.Signed-off-by: Haibo Chen
Reviewed-by: Dong Aisheng
19 Aug, 2019
1 commit
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The AUDIO PLL max support 650M, so the original clk settings violate
spec. In order not to impact audio functionality, let's div the
clk by 2.Signed-off-by: Peng Fan
Reviewed-by: Shengjiu Wang
17 Aug, 2019
1 commit
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On imx8mm and imx8mn pll1_800m is not a parents of qspi, that mux
position connects to pll2_333m instead.Set the assigned-clock-parent to pll1_400m instead so that we can get
80m as expected.Signed-off-by: Leonard Crestez
Reviewed-by: Han Xu
16 Aug, 2019
2 commits
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Support rpmsg audio in imx8mn
Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman
(cherry picked from commit 02f10fd736edbf4c9d144241ec45656f607262c3) -
This reverts commit b49dff663e17302230556745e45eb51b94dc1f0c.
M4 request to control the SAI3 for some customer want to use
the SAI3 + WM8524 for rpmsg playback, so remove the WM8524
sound card in this dtsSigned-off-by: Shengjiu Wang
(cherry picked from commit c4bd981ca2ca28dc2c4b90c6a399876148f0d779)
09 Aug, 2019
3 commits
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There are two sets of CAN regulators that need to be disabled.
Fixes: d7e360899c59 ("MLK-22419 arm64: dts: enable partition reset for imx8dxl phantom board")
Signed-off-by: Leonard Crestez
Reviewed-by: Daniel Baluta -
Enable partition reset function for imx8dxl phantom board.
Use fsl-imx8dxl-phantom-mek-rpmsg.dtb to enable this function.Acked-by: Fugang Duan
Signed-off-by: Clark Wang -
Enable Flexcan on imx8dxl phantom mek.
Acked-by: Fugang Duan
Signed-off-by: Joakim Zhang
08 Aug, 2019
3 commits
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This reverts commit 9811210cb25a98b65be4e3ef35ccaf9c05e0ca83.
No need to remove PD_LVDS1_I2C0 and SC_R_LVDS_1_I2C_0.
Reviewed-by: Anson Huang
Signed-off-by: Clark Wang -
There is an interrupt for each of the 4 slots, so add them
into the 8QXP & 8QM dtb.Signed-off-by: Mirela Rabulea
Reviewed-by: Robert Chiras -
After commit
("MLK-22284-1 dmaengine: fsl-edma-v3: add power domains for each channel")
xen dom0 is broken, need to update dom0 and domu dts for edma.Signed-off-by: Peng Fan
Reviewed-by: Robin Gong
07 Aug, 2019
6 commits
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Remove hardware reset pin for ov5640. Because the level of ov5640
reset pin will be low when system suspend and will be high when
system resume. The action will lead to reset ov5640 to default.
In order to fix the issue, driver load firmware before streaming
on every time, the expense is taking more time.According to OV5640 datasheet, a reset can also be initiated through
the SCCB interface by setting register 0x3008[7] to high. So driver
can remove the hard reset and saving time of loading firmware.Signed-off-by: Guoniu.Zhou
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Add gasket node for imx8mn and replace dispmix GPR with it. And remove
dispmix node since it's not needed any more.Signed-off-by: Guoniu.Zhou
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The dispmix-reset device can be used to control the ISI and
CSIS bus reset and clock enable. So define 'resets' property
for both ISI and CSIS for this purpose which will be used to
replace 'dispmix_gpr' usage.Signed-off-by: Guoniu.Zhou
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Add power domain for MIPI CSI of IMX8MN
Signed-off-by: Guoniu.Zhou
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Because IMX8MN only support one ISI channel, so we need to remove
the others which planned to support before.Signed-off-by: Guoniu.Zhou
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Enable M.2 interface on the phantom-mek board.
- Support WiFi with PCIe interface
- Support Bluetooth with HCI UARTReviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
06 Aug, 2019
4 commits
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Correct the pinmux for SAI1
Remove AUDMIX/ESAI for they are not supported in imx8dxl
Configure fsl,sai-synchronous-rx for SAI1 according to pinmux
Enable ASRC p2p for SAI1Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman -
ENET1 pad ring register for compensation cell and voltage reference
is controlled by pin:
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD- move the pin to enet pin group
- format the pin define as alignment
- move out below two pins to hoggrp
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PADSigned-off-by: Fugang Duan
Acked-by: Richard Zhu -
Use the correct typec node properties according to typec driver
update.Acked-by: Peter Chen
Signed-off-by: Li Jun -
Enable rpmsg on imx8dxl mek board.
Signed-off-by: Richard Zhu
Acked-by: Fugang Duan
05 Aug, 2019
3 commits
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Add DTBs to support imx8dxl phantom mek board.
Signed-off-by: Teo Hall
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The latest reference manual (Rev.0, 06/2019) shows PMC0
and PMC1 have different register offsets, clean them up.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai -
The PMC0 control register is at offset 0x28, not 0x24.
Fix it accordingly.
Signed-off-by: Fabio Estevam
Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
02 Aug, 2019
1 commit
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The patch 4e995ba0a954980 removes the non-exist recources for LVDS1, so
remove the usage of SC_R_LVDS_1_I2C_0/SC_R_LVDS_1_I2C_1 in dts, and
replace pd_lvds1_i2c with pd_lvds1 which is the parent in lvds_i2c node.Reviewed-by: Peng Fan
Signed-off-by: Clark Wang
30 Jul, 2019
1 commit
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It is easy to exploit system by allowing fuse program,
so let's mark as read-only. If pepole wanna fuse program,
just delete this property.Signed-off-by: Peng Fan
Reviewed-by: Ye Li
24 Jul, 2019
2 commits
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In M4 dts, the I2C3 is disabled by default, so the CSI camera sensor
is disabled too. it is not necessary to keep csi_bridge node enabled
anymore, just disable it.Signed-off-by: Jacky Bai
Acked-by: Anson Huang
(cherry picked from commit 93a7f9734d266920d5d1b6f09536021b1777c223) -
Split dma channel power domain from sub-domain of dma customer driver
such as Audio, LPSPI, LPUART.Signed-off-by: Robin Gong
Reviewed-by: S.j. Wang
(cherry picked from commit b76f339fdf91fe44066c2c820e4def07f47d159c)
23 Jul, 2019
1 commit
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At IMX8MN(815) we need to Increase GPU CLK frequency to match the overdrive mode.
The SOC default setting is overdrive mode,and GPU 600M is corresponding to overdrive mode.Signed-off-by: Minjie Zhuang
