29 Dec, 2017
4 commits
-
There were a few fields in the iproc pll data structures that were
holding information that was not true state information.
Using stack variables is sufficient and simplifies the structure.
There are not any functional changes in this commit.Signed-off-by: Lori Hikichi
Signed-off-by: Stephen Boyd -
The iproc plls are capable of doing small rate changes without the
need for a full reset and re-lock procedure. This feature will
allow for small tweaks to the PLL rate to occur smoothly.Signed-off-by: Lori Hikichi
Signed-off-by: Stephen Boyd -
The pll post divider code was using DIV_ROUND_UP when determining the
divider value best suited to produce the target frequency.
Using DIV_ROUND_CLOSEST will give us better divider values when
the division results in a small remainder.
Also, change the post divider clock over to the determine_rate api
instead of round_rate.Signed-off-by: Simran Rai
Signed-off-by: Lori Hikichi
Signed-off-by: Stephen Boyd -
Add the ability for the iproc pll to calculate the pll parameters at
runtime instead of only using predefined tables. This ability allows
the clock users to select from the full range of vco frequencies.
The old method of table based programming is retained so that existing
users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM
will need to be set to enable the new runtime calculation method.
Currently, this is only being enabled for the audio pll.This feature also revealed a problem with the driver using the
round_rate api. The round_rate api does not allow for frequencies larger
than 2^31 to be returned. Those large frequencies are interpreted as an
error code. Therefore, we are moving to the determine_rate api which
solves this problem.Signed-off-by: Simran Rai
Signed-off-by: Lori Hikichi
Signed-off-by: Stephen Boyd
22 Jun, 2017
1 commit
-
Now that this function is called from driver probe routines, it
needs to drop the __init marking because it isn't just called
from init code.Reported-by: Stephen Rothwell
Cc: Sandeep Tripathy
Cc: Anup Patel
Cc: Ray Jui
Cc: Scott Branden
Fixes: 654cdd3229cd ("clk: bcm: Add clocks for Stingray SOC")
Signed-off-by: Stephen Boyd
13 Apr, 2017
1 commit
-
Remove the redundant check of 'rate' in the if statement of the
'pll_set_rate' functionReported-by: David Binderman
Signed-off-by: Ray Jui
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
Signed-off-by: Stephen Boyd
Signed-off-by: Michael Turquette
01 Jul, 2016
1 commit
-
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.Cc: Jon Mason
Cc: Simran Rai
Signed-off-by: Stephen Boyd
Tested-by: Ray Jui
Signed-off-by: Stephen Boyd
30 Jan, 2016
1 commit
-
This patch adds support for Broadcom Cygnus audio PLL and leaf
clocksSigned-off-by: Simran Rai
Reviewed-by: Scott Branden
Signed-off-by: Ray Jui
Signed-off-by: Stephen Boyd
22 Oct, 2015
5 commits
-
* clk-iproc:
clk: iproc: define Broadcom NS2 iProc clock binding
clk: iproc: define Broadcom NSP iProc clock binding
clk: ns2: add clock support for Broadcom Northstar 2 SoC
clk: iproc: Separate status and control variables
clk: iproc: Split off dig_filter
clk: iproc: Add PLL base write function
clk: nsp: add clock support for Broadcom Northstar Plus SoC
clk: iproc: Add PWRCTRL support
clk: cygnus: Convert all macros to all caps
ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled -
Some PLLs have separate registers for Status and Control. The means the
pll_base needs to be split into 2 new variables, so that those PLLs can
specify device tree registers for those independently. Also, add a new
driver flag to identify this presence of the split, and let the driver
know that additional registers need to be used.Signed-off-by: Jon Mason
Signed-off-by: Stephen Boyd -
The PLL loop filter/gain can be located in a separate register on some
SoCs. Split these off into a separate variable, so that an offset can
be added if necessary. Also, make the necessary modifications to the
Cygnus and NSP drivers for this change.Signed-off-by: Jon Mason
Signed-off-by: Stephen Boyd -
All writes to the PLL base address must be flushed if the
IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the
necessary write and reads, we can make sure that any future code which
makes PLL base writes will do the correct thing.Signed-off-by: Jon Mason
Signed-off-by: Stephen Boyd -
Some iProc SoC clocks use a different way to control clock power, via
the PWRDWN bit in the PLL control register. Since the PLL control
register is used to access the PWRDWN bit, there is no need for the
pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL,
has been added to identify this usage. We can use the AON interface to
write the values to enable/disable PWRDOWN.Signed-off-by: Jon Mason
[sboyd@codeaurora.org: Remove useless parentheses]
Signed-off-by: Stephen Boyd
21 Oct, 2015
1 commit
-
This patch affects the clocks that use fractional ndivider in their
PLL output frequency calculation. Instead of 2^20 divide factor, the
clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
integer shift with 2^20 factor.Signed-off-by: Simran Rai
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
Cc: # v4.1+
Signed-off-by: Michael Turquette
03 Jul, 2015
2 commits
-
A 32-bit variable should be type casted to 64-bit before arithmetic
operation and assigning it to a 64-bit variableReported-by: Dan Carpenter
Signed-off-by: Ray Jui
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
Signed-off-by: Stephen Boyd -
of_property_read_string_index takes array of pointers and assign them to
strings read from device tree property. No additional memory allocation
is needed prior to calling of_property_read_string_index. In fact, since
the array of pointers will be re-assigned to other strings, any memory
that it points to prior to calling of_property_read_string_index will be
leakedReported-by: Dan Carpenter
Signed-off-by: Ray Jui
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
Signed-off-by: Stephen Boyd
19 Jun, 2015
1 commit
-
This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed as arugments into the generic iProc PLL and
clock setup functionsDerived from code originally provided by Jonathan Richardson
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
Signed-off-by: Michael Turquette