23 Feb, 2017
2 commits
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In order to save power consumption, turn off pcie clks/regulators
if there is no pcie link at all.
Summit this patch, because of that MLK-12278
doesn't turn off the clks/regulators actually.Signed-off-by: Richard Zhu
-
- move "program correct class for RC" from dw_pcie_host_init()
to dw_pcie_setup_rc(). since this is RC setup, it's
better to contained in dw_pcie_setup_rc function.
Then, RC can be re-setup really by dw_pcie_setup_rc().
- add one store/re-store msi cfg functions. Because that
pcie controller maybe powered off during system suspend,
and the msi data configuration would be lost.
these functions can be used to store/restore the msi data
and msi_enable during the suspend/resume callback.Signed-off-by: Richard Zhu
11 Oct, 2016
3 commits
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Export dw_pcie_readl_rc() and dw_pcie_writel_rc(). Many other drivers can
use these instead of implementing their own versions. No functional change
intended.Signed-off-by: Bjorn Helgaas
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Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.Signed-off-by: Bjorn Helgaas
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The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
allow a driver to override the default DesignWare register accessors.Make the signature of the override functions the same as the default
accessors. This makes the default dw_pcie_readl_rc() and the corresponding
override more structurally similar: both will compute the final register
address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed
the address and passed it to the override.No functional change intended.
Signed-off-by: Bjorn Helgaas
23 Aug, 2016
1 commit
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Most of the platforms have 3 or more viewports. For such platforms, We do
not need to share viewports between IO and CFG. Assign viewport 2 to IO
transactions in such cases.Tested-by: Dong Bo
Signed-off-by: Pratyush Anand
Signed-off-by: Bjorn Helgaas
Acked-by: Rob Herring
18 Aug, 2016
3 commits
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Add support for the new iATU Unroll mechanism that will be used from Core
version 4.80. The new Cores can support either iATU Unroll or the "old"
iATU method, now called Legacy Mode. The driver is perfectly capable of
performing well for both.[bhelgaas: split ATU enable timeout to separate patch]
Signed-off-by: Joao Pinto
Signed-off-by: Bjorn Helgaas -
Move the link wait sleep definitions to the .c file as suggested by
Jisheng Zhang in a previous patch.Signed-off-by: Joao Pinto
Signed-off-by: Bjorn Helgaas
CC: Jisheng Zhang -
dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in
space supplied by the caller. Return the u32 value directly instead.This makes the calling code read better and makes it obvious that the
caller need not initialize the storage. In the following example it isn't
clear whether "val" is initialized before being used:dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
if (val & PCI_COMMAND_MEMORY)
...No functional change intended.
Signed-off-by: Bjorn Helgaas
15 Mar, 2016
1 commit
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Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto
Signed-off-by: Bjorn Helgaas
Acked-by: Pratyush Anand
03 Nov, 2015
4 commits
-
Previously, dw_pcie_host_init() created the PCI host bridge with
pci_common_init_dev(), an ARM-specific function that supplies the ARM-
specific pci_sys_data structure as the PCI "sysdata".Make pcie-designware.c arch-agnostic by reimplementing the functionality of
pci_common_init_dev() directly in dw_pcie_host_init().Note that this changes the bridge sysdata from the ARM pci_sys_data to the
DesignWare pcie_port structure. This doesn't affect the ARM sysdata users
because they are all specific to non-DesignWare host bridges, which will
still have pci_sys_data.[bhelgaas: changelog]
Tested-by: James Morse
Tested-by: Gabriel Fernandez
Tested-by: Minghuan Lian
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
Signed-off-by: Bjorn Helgaas
Acked-by: Pratyush Anand -
Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF
DT parser.[bhelgaas: changelog]
Tested-by: James Morse
Tested-by: Gabriel Fernandez
Tested-by: Minghuan Lian
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: Bjorn Helgaas
Acked-by: Pratyush Anand -
Revert f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated
address").Note that dra7xx_pcie_host_init() now modifies pp->io_base, but we still
need the original value for dw_pcie_setup() in the path below, so this adds
a new io_base_tmp member. It will be removed later when dw_pcie_setup() is
removed.dra7xx_add_pcie_port
dw_pcie_host_init
pp->io_base = range.cpu_addr
pp->io_base_tmp = range.cpu_addr # ops->host_init
dra7xx_pcie_host_init # ops->host_init
pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR # setup
dw_pcie_setup # hw_pci.setup
pci_ioremap_io(..., pp->io_base_tmp) #
Tested-by: Gabriel Fernandez
Tested-by: Minghuan Lian
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
Signed-off-by: Bjorn Helgaas
Acked-by: Pratyush Anand -
Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
split the address into "addr" and "where". The callees assumed "addr" was
32-bit aligned (with zeros in the low two bits) and they used only the low
two bits of "where".Accept the entire address in "addr" and drop the now-redundant "where"
argument. As an example, this replaces this:int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
*val = readb(addr + (where & 1));with this:
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
*val = readb(addr):[bhelgaas: changelog, split access size change to separate patch]
Signed-off-by: Gabriele Paoloni
Signed-off-by: Bjorn Helgaas
19 Sep, 2015
1 commit
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Make get_msi_addr() return phys_addr_t, not u32. This allows the MSI
target address to be above 4GB for 64bit or PAE systems.No functional change for the current 32bit platform users as phys_addr_t
maps to u32 for them.[bhelgaas: changelog]
Signed-off-by: Lucas Stach
Signed-off-by: Bjorn Helgaas
Acked-by: Pratyush Anand
12 Nov, 2014
1 commit
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"msi_chip" isn't very descriptive, so rename it to "msi_controller". That
tells a little more about what it does and is already used in device tree
bindings.No functional change.
[bhelgaas: changelog, change *only* the struct name so it's reviewable]
Suggested-by: Bjorn Helgaas
Signed-off-by: Yijing Wang
Signed-off-by: Bjorn Helgaas
24 Sep, 2014
2 commits
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Add a struct pcie_host_ops .get_msi_data() method for platforms to return
their special MSI message data.Signed-off-by: Minghuan Lian
Signed-off-by: Bjorn Helgaas
Acked-by: Mohit KUMAR -
The struct pcie_host_ops .get_msi_data() method returns the MSI message
address. To accurately express its purpose, rename it to .get_msi_addr().Signed-off-by: Minghuan Lian
Signed-off-by: Bjorn Helgaas
Acked-by: Mohit KUMAR
06 Sep, 2014
1 commit
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The struct pcie_port_info doesn't contain any exclusive information
compared to other elements of struct pcie_port. So, keeping a separate
structure does not seem very logical. Therefore remove this struct and
embed its elements directly into struct pcie_port.Signed-off-by: Pratyush Anand
Signed-off-by: Bjorn Helgaas
Acked-by: Mohit Kumar
05 Sep, 2014
1 commit
-
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach
Signed-off-by: Bjorn Helgaas
Reviewed-by: Pratyush Anand
Acked-by: Mohit Kumar
03 Sep, 2014
1 commit
-
The Keystone PCI controller is based on v3.65 DesignWare hardware. This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.1. No support for ATU port. Any ATU-specific resource handling code is
to be bypassed for v3.65 h/w.2. MSI controller uses application space to implement MSI and 32 MSI
interrupts are multiplexed over 8 IRQs to the host. Hence the code
to process MSI IRQ needs to be different. This patch allows
platform driver to provide its own irq_domain_ops ptr to
irq_domain_add_linear() through an API callback from the DesignWare
core driver.3. MSI interrupt generation requires EP to write to the RC's
application register. So enhance the driver to allow setup of
inbound access to MSI IRQ register as a post scan bus API callback.Signed-off-by: Murali Karicheri
Signed-off-by: Bjorn Helgaas
Reviewed-by: Pratyush Anand
Acked-by: Mohit KUMAR
Acked-by: Jingoo Han
CC: Santosh Shilimkar
CC: Russell King
CC: Grant Likely
CC: Rob Herring
CC: Jingoo Han
CC: Richard Zhu
CC: Kishon Vijay Abraham I
CC: Marek Vasut
CC: Arnd Bergmann
CC: Pawel Moll
CC: Mark Rutland
CC: Ian Campbell
CC: Kumar Gala
CC: Randy Dunlap
CC: Grant Likely
23 Jul, 2014
3 commits
-
DesignWare v3.65 hardware implements MSI controller registers in
application space. This requires updates to the DesignWare core to
support controllers based on this older hardware.Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit
in the application register. Also, v3.65 hardware uses the MSI_IRQ
register in application register space to raise MSI IRQ to the RC from EP.
Current code uses the standard mechanism as per PCI spec. So add
get_msi_data() to get the address of this register so common code can
work on both v3.65 and newer hardware.[bhelgaas: changelog]
Signed-off-by: Murali Karicheri
Signed-off-by: Bjorn Helgaas
Reviewed-by: Pratyush Anand
Acked-by: Mohit Kumar
Acked-by: Jingoo Han
Acked-by: Santosh Shilimkar
CC: Russell King
CC: Grant Likely
CC: Rob Herring
CC: Richard Zhu
CC: Kishon Vijay Abraham I
CC: Marek Vasut
CC: Arnd Bergmann
CC: Pawel Moll
CC: Mark Rutland
CC: Ian Campbell
CC: Kumar Gala
CC: Randy Dunlap
CC: Grant Likely -
DesignWare v3.65 hardware requires application space registers to be
configured to access the remote EP config space.To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops.
[bhelgaas: changelog]
Signed-off-by: Murali Karicheri
Signed-off-by: Bjorn Helgaas
Reviewed-by: Pratyush Anand
Acked-by: Mohit Kumar
Acked-by: Jingoo Han
Acked-by: Santosh Shilimkar
CC: Russell King
CC: Grant Likely
CC: Rob Herring
CC: Richard Zhu
CC: Kishon Vijay Abraham I
CC: Marek Vasut
CC: Arnd Bergmann
CC: Pawel Moll
CC: Mark Rutland
CC: Ian Campbell
CC: Kumar Gala
CC: Randy Dunlap
CC: Grant Likely -
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.This is needed when the dt node is modelled something like this:
axi {
compatible = "simple-bus";
#size-cells = ;
#address-cells = ;
ranges = ;
pcie@51000000 {
reg = , , ;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = ;
#size-cells = ;
ranges = ;
};
};Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Bjorn Helgaas
Reviewed-by: Mohit Kumar
Cc: Jason Gunthorpe
Cc: Jingoo Han
Cc: Marek Vasut
Cc: Arnd Bergmann
03 Jun, 2014
1 commit
-
…/host-tegra' into next
* pci/host-designware:
PCI: designware: Remove unnecessary use of 'conf_lock' spinlock
PCI: designware: Use new OF interrupt mapping when possible
PCI: designware: Fix iATU programming for cfg1, io and mem viewport
PCI: designware: Fix comment for setting number of lanes* pci/host-imx6:
PCI: designware: Split Exynos and i.MX bindings* pci/host-mvebu:
PCI: mvebu: Use '%pa' for printing 'phys_addr_t' type
PCI: mvebu: Remove unnecessary use of 'conf_lock' spinlock
PCI: mvebu: split PCIe BARs into multiple MBus windows when needed
bus: mvebu-mbus: allow several windows with the same target/attribute
bus: mvebu-mbus: Avoid setting an undefined window size
PCI: mvebu: fix off-by-one in the computed size of the mbus windows* pci/host-tegra:
PCI: tegra: Use new OF interrupt mapping when possible
31 May, 2014
1 commit
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On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make
sure we don't bail too early from the IRQ handler.The issue is fairly theoretical as it would require a system setup with a
PCIe switch where one connected device is using legacy INTD and another one
using MSI, but better fix it now.Signed-off-by: Lucas Stach
Signed-off-by: Bjorn Helgaas
Acked-by: Jingoo Han
Acked-by: Richard Zhu
17 Apr, 2014
1 commit
-
Serialization of configuration accesses is provided by 'pci_lock' in
drivers/pci/access.c thus making the driver's 'conf_lock' superfluous.Signed-off-by: Andrew Murray
Signed-off-by: Bjorn Helgaas
Acked-by: Jingoo Han
Acked-by: Richard Zhu
21 Dec, 2013
1 commit
-
The cfg_read/write functions are DesignWare-specific. Add dw_pcie prefix
to avoid collision in global name space.Tested-by: Jingoo Han
Signed-off-by: Pratyush Anand
Signed-off-by: Bjorn Helgaas
Reviewed-by: Jagannadha Sutradharudu Teki
Acked-by: Jingoo Han
09 Oct, 2013
3 commits
-
Without irq_create_mapping(), the correct IRQ number cannot be
provided. In this case, it makes problems such as NULL dereference.
Thus, irq_create_mapping() should be added for MSI.Suggested-by: Kishon Vijay Abraham I
Signed-off-by: Pratyush Anand
Signed-off-by: Jingoo Han
Signed-off-by: Bjorn Helgaas -
The following variables and functions are used only in pcie-designware.c,
so make them static:global_io_offset
dw_pcie_rd_own_conf()
dw_pcie_wr_own_conf()
dw_pcie_setup()
dw_pcie_scan_bus()
dw_pcie_map_irq()Signed-off-by: Bjorn Helgaas
Acked-by: Jingoo Han -
Add header guards to prevent redundant inclusion.
Signed-off-by: Seungwon Jeon
Signed-off-by: Jingoo Han
Signed-off-by: Bjorn Helgaas
26 Sep, 2013
1 commit
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This patch adds support for Message Signaled Interrupt in the
Exynos PCIe driver using Synopsys designware PCIe core IP.Signed-off-by: Siva Reddy Kallam
Signed-off-by: Srikanth T Shivanand
Signed-off-by: Jingoo Han
Signed-off-by: Bjorn Helgaas
Cc: Pratyush Anand
Cc: Mohit KUMAR
13 Aug, 2013
1 commit
-
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.Signed-off-by: Jingoo Han
Signed-off-by: Bjorn Helgaas
Cc: Pratyush Anand
Cc: Mohit KUMAR