02 Apr, 2020
2 commits
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commit 8400ab8896324641243b57fc49b448023c07409a upstream.
The imx SC api strongly assumes that messages are composed out of
4-bytes words but some of our message structs have odd sizeofs.This produces many oopses with CONFIG_KASAN=y.
Fix by marking with __aligned(4).
Fixes: 666aed2d13ee ("clk: imx: scu: add set parent support")
Signed-off-by: Leonard Crestez
Link: https://lkml.kernel.org/r/aad021e432b3062c142973d09b766656eec18fde.1582216144.git.leonard.crestez@nxp.com
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
commit a0ae04a25650fd51b7106e742d27333e502173c6 upstream.
The imx SC api strongly assumes that messages are composed out of
4-bytes words but some of our message structs have odd sizeofs.This produces many oopses with CONFIG_KASAN=y.
Fix by marking with __aligned(4).
Fixes: fe37b4820417 ("clk: imx: add scu clock common part")
Signed-off-by: Leonard Crestez
Link: https://lkml.kernel.org/r/10e97a04980d933b2cfecb6b124bf9046b6e4f16.1582216144.git.leonard.crestez@nxp.com
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman
24 Feb, 2020
1 commit
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[ Upstream commit f60f1c62c3188fcca945581e35e3440ee3fdcc95 ]
If the clk_hw based API returns an error, trying to return the clk from
hw will end up in a NULL pointer dereference. So adding the to_clk
checker and using it inside every clk based macro helper we handle that
case correctly.This to_clk is also temporary and will go away along with the clk based
macro helpers once there is no user that need them anymore.Signed-off-by: Abel Vesa
Signed-off-by: Shawn Guo
Signed-off-by: Sasha Levin
23 Jan, 2020
2 commits
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commit 2e2b928a04bd74ea410da72bd60e1c5b06398276 upstream.
In the latest reference manual Rev.0,06/2019, the DDR clock mux
is extended to 2 bits, and the clock options are also changed,
correct them accordingly.Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver")
Signed-off-by: Anson Huang
Reviewed-by: Fabio Estevam
Signed-off-by: Shawn Guo
Signed-off-by: Greg Kroah-Hartman -
commit 96ac93a7c4bea4eb4186425795c00937d2dd6085 upstream.
In the latest reference manual Rev.0,06/2019, the SCS's option #7
is no longer from upll, it is reserved, update clock driver accordingly.Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver")
Signed-off-by: Anson Huang
Reviewed-by: Fabio Estevam
Signed-off-by: Shawn Guo
Signed-off-by: Greg Kroah-Hartman
18 Jan, 2020
1 commit
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commit 094234fcf46146339caaac8282aa15d225a5911a upstream.
The PLL14xx on imx8m can change the S and K parameter without requiring
a reset and relock of the whole PLL.Fix clk_pll144xx_mp_change register reading and use it for pll1443 as
well since no reset+relock is required on K changes either.Signed-off-by: Leonard Crestez
Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Signed-off-by: Shawn Guo
Signed-off-by: Greg Kroah-Hartman
31 Dec, 2019
3 commits
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commit c3a5fd15ed0c1494435e4e35fbee734ae46b5073 upstream.
The usage of readl_poll_timeout is wrong, the 3rd parameter(cond)
should be "val & LOCK_STATUS" not "val & LOCK_TIMEOUT_US",
It is not check whether the pll locked, LOCK_STATUS reflects the mask,
not LOCK_TIMEOUT_US.Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Cc:
Reviewed-by: Abel Vesa
Signed-off-by: Peng Fan
Signed-off-by: Shawn Guo
Signed-off-by: Greg Kroah-Hartman -
commit 073a01e8d7c23b3efb59a3d4c20aa546f9ec29a9 upstream.
There is a lock to divider in the composite driver, but that's not
enough. lock to gate/mux are also needed to provide exclusive access
to the register.Fixes: d3ff9728134e ("clk: imx: Add imx composite clock")
Signed-off-by: Peng Fan
Cc:
Signed-off-by: Shawn Guo
Signed-off-by: Greg Kroah-Hartman -
commit ed11e31709d7ddb19d4dc451d5bbfb15129f4cad upstream.
There should be a sentinel of ulp_div_table, otherwise _get_table_div
may access data out of the array.Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver")
Signed-off-by: Peng Fan
Cc:
Signed-off-by: Shawn Guo
Signed-off-by: Greg Kroah-Hartman
28 Oct, 2019
1 commit
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During cpu frequency switching the main "CLK_ARM" is reparented to an
intermediate "step" clock. On imx8mm and imx8mn the 24M oscillator is
used for this purpose but it is extremely slow, increasing wakeup
latencies to the point that i2c transactions can timeout and system
becomes unresponsive.Fix by switching the "step" clk to SYS_PLL1_800M, matching the behavior
of imx8m cpufreq drivers in imx vendor tree.This bug was not immediately apparent because upstream arm64 defconfig
uses the "performance" governor by default so no cpufreq transitions
happen.Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")Cc: stable@vger.kernel.org
Signed-off-by: Leonard Crestez
Link: https://lkml.kernel.org/r/f5d2b9c53f1ed5ccb1dd3c6624f56759d92e1689.1571771777.git.leonard.crestez@nxp.com
Acked-by: Shawn Guo
Signed-off-by: Stephen Boyd
18 Sep, 2019
4 commits
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pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.So use EXT_BYPASS bit here.
And drop uneeded set parent, because EXT_BYPASS default is 0.
Suggested-by: Jacky Bai
Reviewed-by: Leonard Crestez
Signed-off-by: Peng Fan
Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd -
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.So use EXT_BYPASS bit here.
And drop uneeded set parent, because EXT_BYPASS default is 0.
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Suggested-by: Jacky Bai
Reviewed-by: Leonard Crestez
Signed-off-by: Peng Fan
Link: https://lkml.kernel.org/r/1568043491-20680-4-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd -
When registering the PLL, unbypass the PLL.
The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
we will expose EXT_BYPASS to clk driver for mux usage, and keep
BYPASS inside pll14xx usage. The PLL has a restriction that
when M/P change, need to RESET/BYPASS pll to avoid glitch, so
we could not expose BYPASS.To make it easy for clk driver usage, unbypass PLL which does
not hurt current function.Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez
Signed-off-by: Peng Fan
Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd -
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.When prepare clock, also need to take care to avoid glitch. So
we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
And add a check if the RESETB is already 0, directly return 0;Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez
Signed-off-by: Peng Fan
Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd
25 Aug, 2019
1 commit
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The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.Signed-off-by: Peng Fan
Reviewed-by: Shengjiu Wang
Signed-off-by: Shawn Guo
19 Aug, 2019
7 commits
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i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo -
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo -
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
Signed-off-by: Shawn Guo -
This is enabled by default but if it's not explicitly defined and marked
as critical then its parent might get turned off.Signed-off-by: Leonard Crestez
Signed-off-by: Shawn Guo -
* Replace to audio_pll2_clk with audio_pll2_out
* Replace sys3_pll2_out with sys_pll3_out
* Replace sys1_pll_40m with sys_pll1_40m
* qspi parent[2] is sys_pll2_333m not sys_pll1_800mFixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Leonard Crestez
Signed-off-by: Shawn Guo -
* There is no video_pll2 on imx8mm, replace with dummy
* Replace reference to sys_pll3_clk with sys_pll3_out
* qspi parent[2] is sys_pll2_333m not sys_pll1_800mFixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Leonard Crestez
Signed-off-by: Shawn Guo -
The "sys3_pll2_out" CLK was removed in refactoring so all references
need to be updated to "sys3_pll_out"Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Leonard Crestez
Signed-off-by: Shawn Guo
12 Aug, 2019
2 commits
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When of_clk_add_provider failed, all clks should be unregistered.
Signed-off-by: Anson Huang
Reviewed-by: Daniel Baluta
Signed-off-by: Shawn Guo -
When of_clk_add_provider failed, all clks should be unregistered.
Signed-off-by: Anson Huang
Reviewed-by: Daniel Baluta
Signed-off-by: Shawn Guo
03 Aug, 2019
16 commits
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Initially, the TMU_ROOT clock was marked as critical, which automatically
made the AHB clock to stay always on. Since the TMU_ROOT clock is not
marked as critical anymore, following commit:"clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT"
all the clocks that derive from ipg_root clock (and implicitly ahb clock)
would also have to enable, along with their own gate, the AHB clock.But considering that AHB is actually a bus that has to be always on, we mark
it as critical in the clock provider driver and then all the clocks that
derive from it can be controlled through the dedicated per IP gate which
follows after the ipg_root clock.Signed-off-by: Abel Vesa
Tested-by: Daniel Baluta
Signed-off-by: Shawn Guo -
Call imx_register_uart_clocks() API to keep uart clocks enabled
when earlyprintk or earlycon is active.Signed-off-by: Anson Huang
Reviewed-by: Abel Vesa
Signed-off-by: Shawn Guo -
imx_register_uart_clocks_hws() function is NOT implemented
at all, remove it.Signed-off-by: Anson Huang
Acked-by: Uwe Kleine-König
Reviewed-by: Abel Vesa
Signed-off-by: Shawn Guo -
Earlycon's clock could be disabled during kernel boot up,
if earlycon is enabled and its clock is gated, then kernel
boot up will fail. Make sure earlycon's clock is enabled
during kernel boot up.Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo -
There is no strong reason for this to use CLK_OF_DECLARE instead
of being a platform driver. Plus, this will now be aligned with the
other i.MX8M clock drivers which are platform drivers.In order to make the clock provider a platform driver
all the data and code needs to be outside of .init section.Signed-off-by: Abel Vesa
Acked-by: Stephen Boyd
Signed-off-by: Shawn Guo -
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.Cc:
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan
Acked-by: Abel Vesa
Signed-off-by: Shawn Guo -
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo -
i.MX8MM has no sys3_pll2_out clock, PWM3 clock's mux option #4
should be sys_pll3_out, sys3_pll2_out is a typo, fix it.Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo -
Now that the i.MX6 and i.MX7 clock drivers have been switched to clk_hw based,
we can remove the clk based API that is not used by any i.MX clock driver.The following APIs are going away now:
- imx_clk_busy_divider
- imx_clk_busy_mux
- imx_clk_fixup_divider
- imx_clk_fixup_mux
- imx_clk_mux_ldb
- imx_clk_gate_dis_flags
- imx_clk_gate_flagsSigned-off-by: Abel Vesa
Signed-off-by: Shawn Guo -
Per latest imx8mq datasheet of CCM, the parent of usb1_ctrl_root_clk
and usb2_ctrl_root_clk is usb_bus.Signed-off-by: Li Jun
Reviewed-by: Abel Vesa
Signed-off-by: Shawn Guo -
IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver
should manage this clock, so no need to have CLK_IS_CRITICAL flag
set.Signed-off-by: Anson Huang
Reviewed-by: Abel Vesa
Acked-by: Stephen Boyd
Signed-off-by: Shawn Guo -
Rename 'share_count_dcss' to 'share_count_disp', since the
DCSS module does not exist on imx8mm platform. So rename it
to avoid any unnecessary confusion.Signed-off-by: Fancy Fang
Signed-off-by: Shawn Guo -
Per latest imx8mm datasheet of CCM, the parent of usb1_ctrl_root_clk
should be usb_bus.Signed-off-by: Li Jun
Signed-off-by: Shawn Guo -
i.MX8QXP contains Hifi4 DSP. There are four clocks
associated with DSP:
* dsp_lpcg_core_clk
* dsp_lpcg_ipg_clk
* dsp_lpcg_adb_aclk
* ocram_lpcg_ipg_clkSigned-off-by: Daniel Baluta
Reviewed-by: Dong Aisheng
Signed-off-by: Shawn Guo -
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo -
For i.MX clock drivers probe fail case, clks should be unregistered
in the return path, this patch adds a common API for i.MX clock
drivers to unregister clocks when fail.Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo
