08 Aug, 2019
1 commit
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Extend the probe by index API in common code to be used
by other qcom clock controller.Signed-off-by: Govind Singh
Signed-off-by: Stephen Boyd
22 Feb, 2019
1 commit
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Several clock controller drivers define a list of clk_hw devices, and then
register those devices in probe() before using common code to process the
rest of initialization. Extend the common code to accept a list of clk_hw
devices to process, thus eliminating many duplicate implementations.Signed-off-by: Jeffrey Hugo
Suggested-by: Stephen Boyd
Reviewed-by: Vinod Koul
Tested-by: Vinod Koul
Signed-off-by: Stephen Boyd
26 Jul, 2018
1 commit
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SPDX headers updated for common/branch/pll/regmap files.
Signed-off-by: Taniya Das
Signed-off-by: Stephen Boyd
22 Dec, 2017
1 commit
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Currently the driver assumes the register configuration value
is identical to its index in the parent map. This patch adds
the parent map field in regmap mux clock node which contains
the mapping of parent index with actual register configuration
value. If regmap node contains this parent map then the
configuration value will be taken from this
parent map instead of simply writing the index value.Signed-off-by: Abhishek Sahu
Signed-off-by: Stephen Boyd
24 Nov, 2016
1 commit
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The default behaviour with clk_rcg2_ops is for the
clk_round_rate()/clk_set_rate() to return/set a ceil clock
rate closest to the requested rate by looking up the corresponding
frequency table.
However, we do have some instances (mainly sdcc on various platforms)
of clients expecting a clk_set_rate() to set a floor value instead.
Add a new clk_rcg2_floor_ops to handle this for such specific
rcg instancesSigned-off-by: Rajendra Nayak
Signed-off-by: Ritesh Harjani
Signed-off-by: Stephen Boyd
02 Nov, 2016
1 commit
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The votable alpha PLLs need to have the fsm mode enabled as part
of the initialization. The sequence seems to be the same as used
by clk-pll, so move the function which does this into a common
place and reuse it for the clk-alpha-pllSigned-off-by: Rajendra Nayak
Signed-off-by: Taniya Das
Signed-off-by: Stephen Boyd
17 Nov, 2015
1 commit
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We want to put the XO board clocks into the dt files, but we also
need to be backwards compatible with an older dtb. Add an API to
the common code to do this. This also makes a place for us to
handle the case when the RPM clock driver is enabled and we don't
want to register the fixed factor clock.Cc: Georgi Djakov
Signed-off-by: Stephen Boyd
09 Oct, 2015
1 commit
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Now that qcom_cc_remove() is a nop, drop calls to
qcom_cc_remove() and any empty driver remove functions.Cc: Rajendra Nayak
Signed-off-by: Stephen Boyd
17 Sep, 2015
1 commit
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The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd
24 Mar, 2015
1 commit
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In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
- Define a parent_map struct to map the relations between PLL source index
and register configuration value.
- Add a qcom_find_src_index() function for finding the index of a clock
matching the specific PLL configuration.
- Update the {set,get}_parent RCG functions use the newly introduced
parent_map struct.
- Convert all existing drivers to the new parent_map tables.Signed-off-by: Georgi Djakov
Signed-off-by: Stephen Boyd
23 Sep, 2014
1 commit
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There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.Cc: Mike Turquette
Signed-off-by: Stephen Boyd
16 Jul, 2014
1 commit
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Sometimes we need to program PLLs with a fixed rate
configuration during driver probe. Doing this after we register
the PLLs with the clock framework causes the common clock
framework to assume the rate of the PLLs are 0. This causes all
sorts of problems for rate recalculations because the common
clock framework caches the rate once at registration time unless
a flag is set to always recalculate the rates.Split the qcom_cc_probe() function into two pieces, map and
everything else, so that drivers which need to configure some
PLL rates or otherwise twiddle bits in the clock controller can
do so before registering clocks. This allows us to properly
detect the rates of PLLs that are programmed at boot.Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code"
Signed-off-by: Stephen Boyd
01 May, 2014
1 commit
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Most of the probe code is the same between all the different
clock controllers. Consolidate the code into a common.c file.
This makes changes to the common probe parts easier and reduces
chances for bugs.Signed-off-by: Stephen Boyd
Signed-off-by: Mike Turquette