Eric Lee / smarc-fsl-linux-kernel

31 Jul, 2019

1 commit

  • 091c6104a   dma: Drop JZ4740 driver ... Browse Code »

    The newer and better JZ4780 driver is now used to provide DMA
    functionality on the JZ4740.

    Signed-off-by: Paul Cercueil
    Tested-by: Artur Rojek
    Acked-by: Vinod Koul
    Signed-off-by: Paul Burton

    Paul Cercueil
     

10 Jun, 2019

1 commit

  • e63d79d1f   dmaengine: Add Synopsys eDMA IP core driver ... Browse Code »

    Add Synopsys PCIe Endpoint eDMA IP core driver to kernel.

    This IP is generally distributed with Synopsys PCIe Endpoint IP (depends
    of the use and licensing agreement).

    This core driver, initializes and configures the eDMA IP using vma-helpers
    functions and dma-engine subsystem.

    This driver can be compile as built-in or external module in kernel.

    To enable this driver just select DW_EDMA option in kernel configuration,
    however it requires and selects automatically DMA_ENGINE and
    DMA_VIRTUAL_CHANNELS option too.

    In order to transfer data from point A to B as fast as possible this IP
    requires a dedicated memory space containing linked list of elements.

    All elements of this linked list are continuous and each one describes a
    data transfer (source and destination addresses, length and a control
    variable).

    For the sake of simplicity, lets assume a memory space for channel write
    0 which allows about 42 elements.

    +---------+
    | Desc #0 |-+
    +---------+ |
    V
    +----------+
    | Chunk #0 |-+
    | CB = 1 | | +----------+ +-----+ +-----------+ +-----+
    +----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp |
    | +----------+ +-----+ +-----------+ +-----+
    V
    +----------+
    | Chunk #1 |-+
    | CB = 0 | | +-----------+ +-----+ +-----------+ +-----+
    +----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp |
    | +-----------+ +-----+ +-----------+ +-----+
    V
    +----------+
    | Chunk #2 |-+
    | CB = 1 | | +-----------+ +-----+ +------------+ +-----+
    +----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp |
    | +-----------+ +-----+ +------------+ +-----+
    V
    +----------+
    | Chunk #3 |-+
    | CB = 0 | | +------------+ +-----+ +------------+ +-----+
    +----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp |
    +------------+ +-----+ +------------+ +-----+

    Legend:
    - Linked list, also know as Chunk
    - Linked list element*, also know as Burst *CB*, also know as Change Bit,
    it's a control bit (and typically is toggled) that allows to easily
    identify and differentiate between the current linked list and the
    previous or the next one.
    - LLP, is a special element that indicates the end of the linked list
    element stream also informs that the next CB should be toggle

    On every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or
    even Burst #129) is set some flags on their control variable (RIE and
    LIE bits) that will trigger the send of "done" interruption.

    On the interruptions callback, is decided whether to recycle the linked
    list memory space by writing a new set of Bursts elements (if still
    exists Chunks to transfer) or is considered completed (if there is no
    Chunks available to transfer).

    On scatter-gather transfer mode, the client will submit a scatter-gather
    list of n (on this case 130) elements, that will be divide in multiple
    Chunks, each Chunk will have (on this case 42) a limited number of
    Bursts and after transferring all Bursts, an interrupt will be
    triggered, which will allow to recycle the all linked list dedicated
    memory again with the new information relative to the next Chunk and
    respective Burst associated and repeat the whole cycle again.

    On cyclic transfer mode, the client will submit a buffer pointer, length
    of it and number of repetitions, in this case each burst will correspond
    directly to each repetition.

    Each Burst can describes a data transfer from point A(source) to point
    B(destination) with a length that can be from 1 byte up to 4 GB. Since
    dedicated the memory space where the linked list will reside is limited,
    the whole n burst elements will be organized in several Chunks, that
    will be used later to recycle the dedicated memory space to initiate a
    new sequence of data transfers.

    The whole transfer is considered has completed when it was transferred
    all bursts.

    Currently this IP has a set well-known register map, which includes
    support for legacy and unroll modes. Legacy mode is version of this
    register map that has multiplexer register that allows to switch
    registers between all write and read channels and the unroll modes
    repeats all write and read channels registers with an offset between
    them. This register map is called v0.

    The IP team is creating a new register map more suitable to the latest
    PCIe features, that very likely will change the map register, which this
    version will be called v1. As soon as this new version is released by
    the IP team the support for this version in be included on this driver.

    According to the logic, patches 1, 2 and 3 should be squashed into 1
    unique patch, but for the sake of simplicity of review, it was divided
    in this 3 patches files.

    Signed-off-by: Gustavo Pimentel
    Cc: Vinod Koul
    Cc: Dan Williams
    Cc: Andy Shevchenko
    Cc: Russell King
    Cc: Joao Pinto
    Signed-off-by: Vinod Koul

    Gustavo Pimentel
     

07 Jan, 2019

1 commit

24 Nov, 2018

1 commit

11 Sep, 2018

2 commits

09 Aug, 2018

1 commit

25 Apr, 2018

1 commit

10 Apr, 2018

1 commit

27 Mar, 2018

1 commit

  • 548c4597e   dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC ... Browse Code »

    MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has
    a single ring is dedicated to memory-to-memory transfer through ring based
    descriptor management.

    Even though there is only one physical ring available inside HSDMA, the
    driver can be easily extended to the support of multiple virtual channels
    processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort.

    Signed-off-by: Sean Wang
    Cc: Randy Dunlap
    Cc: Fengguang Wu
    Cc: Julia Lawall
    Signed-off-by: Vinod Koul

    Sean Wang
     

19 Mar, 2018

1 commit

15 Nov, 2017

1 commit

  • 23c258763   Merge tag 'dmaengine-4.15-rc1' of git://git.infradead.org/users/vkoul/slave-dma ... Browse Code »

    Pull dmaengine updates from Vinod Koul:
    "Updates for this cycle include:

    - new driver for Spreadtrum dma controller, ST MDMA and DMAMUX
    controllers

    - PM support for IMG MDC drivers

    - updates to bcm-sba-raid driver and improvements to sun6i driver

    - subsystem conversion for:
    - timers to use timer_setup()
    - remove usage of PCI pool API
    - usage of %p format specifier

    - minor updates to bunch of drivers"

    * tag 'dmaengine-4.15-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (49 commits)
    dmaengine: ti-dma-crossbar: Correct am335x/am43xx mux value type
    dmaengine: dmatest: warn user when dma test times out
    dmaengine: Revert "rcar-dmac: use TCRB instead of TCR for residue"
    dmaengine: stm32_mdma: activate pack/unpack feature
    dmaengine: at_hdmac: Remove unnecessary 0x prefixes before %pad
    dmaengine: coh901318: Remove unnecessary 0x prefixes before %pad
    MAINTAINERS: Step down from a co-maintaner of DW DMAC driver
    dmaengine: pch_dma: Replace PCI pool old API
    dmaengine: Convert timers to use timer_setup()
    dmaengine: sprd: Add Spreadtrum DMA driver
    dt-bindings: dmaengine: Add Spreadtrum SC9860 DMA controller
    dmaengine: sun6i: Retrieve channel count/max request from devicetree
    dmaengine: Build bcm-sba-raid driver as loadable module for iProc SoCs
    dmaengine: bcm-sba-raid: Use common GPL comment header
    dmaengine: bcm-sba-raid: Use only single mailbox channel
    dmaengine: bcm-sba-raid: serialize dma_cookie_complete() using reqs_lock
    dmaengine: pl330: fix descriptor allocation fail
    dmaengine: rcar-dmac: use TCRB instead of TCR for residue
    dmaengine: sun6i: Add support for Allwinner A64 and compatibles
    arm64: allwinner: a64: Add devicetree binding for DMA controller
    ...

    Linus Torvalds
     

14 Nov, 2017

1 commit

02 Nov, 2017

1 commit

  • b24413180   License cleanup: add SPDX GPL-2.0 license identifier to files with no license ... Browse Code »

    Many source files in the tree are missing licensing information, which
    makes it harder for compliance tools to determine the correct license.

    By default all files without license information are under the default
    license of the kernel, which is GPL version 2.

    Update the files which contain no license information with the 'GPL-2.0'
    SPDX license identifier. The SPDX identifier is a legally binding
    shorthand, which can be used instead of the full boiler plate text.

    This patch is based on work done by Thomas Gleixner and Kate Stewart and
    Philippe Ombredanne.

    How this work was done:

    Patches were generated and checked against linux-4.14-rc6 for a subset of
    the use cases:
    - file had no licensing information it it.
    - file was a */uapi/* one with no licensing information in it,
    - file was a */uapi/* one with existing licensing information,

    Further patches will be generated in subsequent months to fix up cases
    where non-standard license headers were used, and references to license
    had to be inferred by heuristics based on keywords.

    The analysis to determine which SPDX License Identifier to be applied to
    a file was done in a spreadsheet of side by side results from of the
    output of two independent scanners (ScanCode & Windriver) producing SPDX
    tag:value files created by Philippe Ombredanne. Philippe prepared the
    base worksheet, and did an initial spot review of a few 1000 files.

    The 4.13 kernel was the starting point of the analysis with 60,537 files
    assessed. Kate Stewart did a file by file comparison of the scanner
    results in the spreadsheet to determine which SPDX license identifier(s)
    to be applied to the file. She confirmed any determination that was not
    immediately clear with lawyers working with the Linux Foundation.

    Criteria used to select files for SPDX license identifier tagging was:
    - Files considered eligible had to be source code files.
    - Make and config files were included as candidates if they contained >5
    lines of source
    - File already had some variant of a license header in it (even if
    Reviewed-by: Philippe Ombredanne
    Reviewed-by: Thomas Gleixner
    Signed-off-by: Greg Kroah-Hartman

    Greg Kroah-Hartman
     

24 Oct, 2017

1 commit

08 Oct, 2017

1 commit

  • a4ffb13c8   dmaengine: Add STM32 MDMA driver ... Browse Code »

    This patch adds the driver for the STM32 MDMA controller.

    Master Direct memory access (MDMA) is used in order to provide high-speed
    data transfer between memory and memory or between peripherals and memory.

    MDMA controller provides a master AXI interface for main memory and
    peripheral registers access (system access port) and a master AHB
    interface only for Cortex-M7 TCM memory access (TCM access port).

    MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2).
    It offers up to 64 channels, each dedicated to managing memory access
    requests from one of the DMA stream memory buffer or other peripherals
    (w/ integrated FIFO).

    Signed-off-by: M'boumba Cedric Madianga
    Signed-off-by: Pierre-Yves MORDRET
    Signed-off-by: Vinod Koul

    Pierre-Yves MORDRET
     

27 Sep, 2017

1 commit

  • df7e762db   dmaengine: Add STM32 DMAMUX driver ... Browse Code »

    This patch implements the STM32 DMAMUX driver.

    The DMAMUX request multiplexer allows routing a DMA request line between
    the peripherals and the DMA controllers of the product. The routing
    function is ensured by a programmable multi-channel DMA request line
    multiplexer. Each channel selects a unique DMA request line,
    unconditionally or synchronously with events from its DMAMUX
    synchronization inputs. The DMAMUX may also be used as a DMA request
    generator from programmable events on its input trigger signals

    Signed-off-by: M'boumba Cedric Madianga
    Signed-off-by: Pierre-Yves MORDRET
    Signed-off-by: Vinod Koul

    Pierre-Yves MORDRET
     

19 Jul, 2017

1 commit

  • a85c6f1b2   dmaengine: Add driver for Altera / Intel mSGDMA IP core ... Browse Code »

    This driver adds support for the Altera / Intel modular Scatter-Gather
    Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux
    DMAengine subsystem. Currently it supports the following op modes:

    - DMA_MEMCPY
    - DMA_SG
    - DMA_SLAVE

    This implementation has been tested on an Altera Cyclone FPGA connected
    via PCIe, both on an ARM and an x86 platform.

    Signed-off-by: Stefan Roese
    Cc: Vinod Koul
    Signed-off-by: Vinod Koul

    Stefan Roese
     

16 May, 2017

1 commit

  • 743e1c8ff   dmaengine: Add Broadcom SBA RAID driver ... Browse Code »

    The Broadcom stream buffer accelerator (SBA) provides offloading
    capabilities for RAID operations. This SBA offload engine is
    accessible via Broadcom SoC specific ring manager.

    This patch adds Broadcom SBA RAID driver which provides one
    DMA device with RAID capabilities using one or more Broadcom
    SoC specific ring manager channels. The SBA RAID driver in its
    current shape implements memcpy, xor, and pq operations.

    Signed-off-by: Anup Patel
    Reviewed-by: Ray Jui
    Acked-by: Dan Williams
    Signed-off-by: Vinod Koul

    Anup Patel
     

02 Jan, 2017

1 commit

18 Oct, 2016

1 commit

  • 6b4cd727e   dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support ... Browse Code »

    This patch adds support for the Flexible Direct Memory Access (FDMA) core
    driver. The FDMA is a slim core CPU with a dedicated firmware.
    It is a general purpose DMA controller capable of supporting 16
    independent DMA channels. Data moves maybe from memory to memory
    or between memory and paced latency critical real time targets and it
    is found on al STi based chipsets.

    Signed-off-by: Ludovic Barre
    Signed-off-by: Peter Griffin
    Signed-off-by: Vinod Koul

    Peter Griffin
     

12 Jul, 2016

1 commit

  • 19a340b1a   dmaengine: mv_xor_v2: new driver ... Browse Code »

    The new mv_xor_v2 driver supports the XOR engines found in the 64-bits
    ARM from Marvell of the Armada 7K and Armada 8K family. This XOR
    engine is a completely new hardware block, entirely different from the
    one used on previous Marvell Armada platforms, which use the existing
    mv_xor driver.

    Signed-off-by: Thomas Petazzoni
    Signed-off-by: Vinod Koul

    Thomas Petazzoni
     

13 May, 2016

1 commit

  • f46b19579   dmaengine: tegra-adma: Add support for Tegra210 ADMA ... Browse Code »

    Add support for the Tegra210 Audio DMA controller that is used for
    transferring data between system memory and the Audio sub-system.
    The driver only supports cyclic transfers because this is being solely
    used for audio.

    This driver is based upon the work by Dara Ramesh .

    Signed-off-by: Jon Hunter
    Signed-off-by: Vinod Koul

    Jon Hunter
     

11 Mar, 2016

1 commit

16 Nov, 2015

1 commit

24 Sep, 2015

1 commit

  • 9ab8b4e7c   dmaengine: idma: rename to INTEL_IDMA64 ... Browse Code »

    the symbol CONFIG_IDMA64 should rather be CONFIG_INTEL_IDMA64 to conform to
    rest of the intel dmaengine drivers. This was found after sorting the
    entries and trying to place this odd one

    Suggested-by: Linus Torvalds
    Acked-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Vinod Koul
     

05 Sep, 2015

1 commit

  • 352712274   Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma ... Browse Code »

    Pull dmaengine updates from Vinod Koul:
    "This time we have aded a new capability for scatter-gathered memset
    using dmaengine APIs. This is supported in xdmac & hdmac drivers

    We have added support for reusing descriptors for examples like video
    buffers etc. Driver will follow

    The behaviour of descriptor ack has been clarified and documented

    New devices added are:
    - dma controller in sun[457]i SoCs
    - lpc18xx dmamux
    - ZTE ZX296702 dma controller
    - Analog Devices AXI-DMAC DMA controller
    - eDMA support for dma-crossbar
    - imx6sx support in imx-sdma driver
    - imx-sdma device to device support

    Other:
    - jz4780 fixes
    - ioatdma large refactor and cleanup for removal of ioat v1 and v2
    which is deprecated and fixes
    - ACPI support in X-Gene DMA engine driver
    - ipu irq fixes
    - mvxor fixes
    - minor fixes spread thru drivers"

    [ The Kconfig and Makefile entries got re-sorted alphabetically, and I
    handled the conflict with the new Intel integrated IDMA driver by
    slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in
    order to keep the Intel entries together. I think it might be a good
    idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make
    the sorting be a true sort, not this mismash.

    Also, this merge disables the COMPILE_TEST for the sun4i DMA
    controller, because it does not compile cleanly at all. - Linus ]

    * tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits)
    dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs
    dmaengine :ipu: change ipu_irq_handler() to remove compile warning
    dmaengine: ioatdma: Fix variable array length
    dmaengine: ioatdma: fix sparse "error" with prep lock
    dmaengine: hdmac: Add memset capabilities
    dmaengine: sort the sh Makefile
    dmaengine: sort the sh Kconfig
    dmaengine: sort the dw Kconfig
    dmaengine: sort the Kconfig
    dmaengine: sort the makefile
    drivers/dma: make mv_xor.c driver explicitly non-modular
    dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller
    devicetree: Add bindings documentation for Analog Devices AXI-DMAC
    dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests
    dmaengine: ioatdma: fix coccinelle warning
    dmaengine: ioatdma: fix zero day warning on incompatible pointer type
    dmaengine: tegra-apb: Simplify locking for device using global pause
    dmaengine: tegra-apb: Remove unnecessary return statements and variables
    dmaengine: tegra-apb: Avoid unnecessary channel base address calculation
    dmaengine: tegra-apb: Remove unused variables
    ...

    Linus Torvalds
     

24 Aug, 2015

1 commit

  • 7e97229b3   dmaengine: sort the makefile ... Browse Code »

    dmaengine makefile grew over the years, unfortunately without any
    order to it. So order by core, dmatest and driver sections and
    sort these sections alphabetically

    Signed-off-by: Vinod Koul

    Vinod Koul
     

23 Aug, 2015

2 commits

  • 0e3b67b34   dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller ... Browse Code »

    Add support for the Analog Devices AXI-DMAC DMA controller. This controller
    is a soft peripheral that can be instantiated in a FPGA and is often used
    in Analog Devices' reference designs for FPGA platforms.

    The peripheral has various configuration options that can be selected at
    synthesis time and influence the supported features of the instantiated
    peripheral, those options are represented as device-tree properties to
    allow the driver to behave accordingly.

    The peripheral has a zero latency architecture, which means it is possible
    to switch from one to the next descriptor without any delay. This is
    archived by having a internal queue which can hold multiple descriptors.
    The driver supports this, which means it will submit new descriptors
    directly to the hardware until the queue is full and not wait for a
    descriptor to complete before the next one is submitted. Interrupts are
    used for the descriptor queue flow control.

    Currently the driver supports SG, cyclic and interleaved slave DMA.

    Signed-off-by: Lars-Peter Clausen
    Signed-off-by: Vinod Koul

    Lars-Peter Clausen
     
  • b2b48ac4c   Merge branch 'topic/zxdma' into for-linus Browse Code »
    Vinod Koul
     

20 Aug, 2015

1 commit

  • b096c1377   dmaengine: sun4i: Add support for the DMA engine on sun[457]i SoCs ... Browse Code »

    This patch adds support for the DMA engine present on Allwinner A10,
    A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
    and dedicated. The main difference is in the mode of operation;
    while a single normal channel may be operating at any given time,
    dedicated channels may operate simultaneously provided there is no
    overlap of source or destination.

    Hardware documentation can be found on A10 User Manual (section 12), A13
    User Manual (section 14) and A20 User Manual (section 1.12)

    Signed-off-by: Emilio López
    Signed-off-by: Hans de Goede
    Signed-off-by: Maxime Ripard
    Signed-off-by: Vinod Koul

    Emilio López
     

19 Aug, 2015

1 commit

  • e5f4ae84b   dmaengine: add driver for lpc18xx dmamux ... Browse Code »

    Add support for DMA on NXP LPC18xx/43xx platforms which has
    a multiplexer in front of the PL080 dma request lines.

    The mux is a single register in the LPC18xx/43xx CREG block
    and can multiplex up to 4 request lines to each of the 16
    lines on the PL080.

    Signed-off-by: Joachim Eastwood
    Signed-off-by: Vinod Koul

    Joachim Eastwood
     

28 Jul, 2015

1 commit

  • 667dfed98   dmaengine: add a driver for Intel integrated DMA 64-bit ... Browse Code »

    Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
    LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
    usage on each host controller independently.

    While it has similarities with Synopsys DesignWare DMA, the following
    distinctions doesn't allow to use the existing driver:
    - 64-bit mode with corresponding changes in Hardware Linked List data structure
    - many slight differences in the channel registers

    Moreover this driver is based on the DMA virtual channels framework that helps
    to make the driver cleaner and easy to understand.

    Signed-off-by: Andy Shevchenko
    Acked-by: Vinod Koul
    Signed-off-by: Lee Jones

    Andy Shevchenko
     

16 Jul, 2015

1 commit

25 Jun, 2015

1 commit

26 May, 2015

1 commit

  • a57e16cf0   dmaengine: pxa: add pxa dmaengine driver ... Browse Code »

    This is a new driver for pxa SoCs, which is also compatible with the former
    mmp_pdma.

    The rationale behind a new driver (as opposed to incremental patching) was :

    - the new driver relies on virt-dma, which obsoletes all the internal
    structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
    functions

    - mmp_pdma allocates dma coherent descriptors containing not only hardware
    descriptors but linked list information
    The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
    dma pool allocated memory. This changes completely the way descriptors are
    handled

    - the architecture behind the interrupt/tasklet management was rewritten to be
    more conforming to virt-dma

    - the buffers alignment is handled differently
    The former driver assumed that the DMA channel stopped between each
    descriptor. The new one chains descriptors to let the channel running. This
    is a necessary guarantee for real-time high bandwidth usecases such as video
    capture on "old" architectures such as pxa.

    - hot chaining / cold chaining / no chaining
    Whenever possible, submitting a descriptor "hot chains" it to a running
    channel. There is still no guarantee that the descriptor will be issued, as
    the channel might be stopped just before the descriptor is submitted. Yet
    this allows to submit several video buffers, and resubmit a buffer while
    another is under handling.
    As before, dma_async_issue_pending() is the only guarantee to have all the
    buffers issued.
    When an alignment issue is detected (ie. one address in a descriptor is not
    a multiple of 8), if the already running channel is in "aligned mode", the
    channel will stop, and restarted in "misaligned mode" to finished the issued
    list.

    - descriptors reusing
    A submitted, issued and completed descriptor can be reused, ie resubmitted if
    it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
    resources release will in this case release that buffer.
    This allows a rolling ring of buffers to be reused, where there are several
    thousands of hardware descriptors used (video buffer for example).

    Additionally, a set of more casual features is introduced :
    - debugging traces
    - lockless way to know if a descriptor is terminated or not

    The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
    with dmatest, pxa_camera and pxamci.

    Signed-off-by: Robert Jarzmik
    Signed-off-by: Vinod Koul

    Robert Jarzmik
     

14 May, 2015

1 commit

25 Apr, 2015

1 commit

  • d6a4c0e5d   Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma ... Browse Code »

    Pull slave-dmaengine updates from Vinod Koul:

    - new drivers for:
    - Ingenic JZ4780 controller
    - APM X-Gene controller
    - Freescale RaidEngine device
    - Renesas USB Controller

    - remove device_alloc_chan_resources dummy handlers

    - sh driver cleanups for peri peri and related emmc and asoc patches
    as well

    - fixes and enhancements spread over the drivers

    * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (59 commits)
    dmaengine: dw: don't prompt for DW_DMAC_CORE
    dmaengine: shdmac: avoid unused variable warnings
    dmaengine: fix platform_no_drv_owner.cocci warnings
    dmaengine: pch_dma: fix memory leak on failure path in pch_dma_probe()
    dmaengine: at_xdmac: unlock spin lock before return
    dmaengine: xgene: devm_ioremap() returns NULL on error
    dmaengine: xgene: buffer overflow in xgene_dma_init_channels()
    dmaengine: usb-dmac: Fix dereferencing freed memory 'desc'
    dmaengine: sa11x0: report slave capabilities to upper layers
    dmaengine: vdma: Fix compilation warnings
    dmaengine: fsl_raid: statify fsl_re_chan_probe
    dmaengine: Driver support for FSL RaidEngine device.
    dmaengine: xgene_dma_init_ring_mngr() can be static
    Documentation: dma: Add documentation for the APM X-Gene SoC DMA device DTS binding
    arm64: dts: Add APM X-Gene SoC DMA device and DMA clock DTS nodes
    dmaengine: Add support for APM X-Gene SoC DMA engine driver
    dmaengine: usb-dmac: Add Renesas USB DMA Controller (USB-DMAC) driver
    dmaengine: renesas,usb-dmac: Add device tree bindings documentation
    dmaengine: edma: fixed wrongly initialized data parameter to the edma callback
    dmaengine: ste_dma40: fix implicit conversion
    ...

    Linus Torvalds
     

22 Apr, 2015

1 commit

  • 41d5e08ea   Merge tag 'tty-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty ... Browse Code »

    Pull tty/serial updates from Greg KH:
    "Here's the big tty/serial driver update for 4.1-rc1.

    It was delayed for a bit due to some questions surrounding some of the
    console command line parsing changes that are in here. There's still
    one tiny regression for people who were previously putting multiple
    console command lines and expecting them all to be ignored for some
    odd reason, but Peter is working on fixing that. If not, I'll send a
    revert for the offending patch, but I have faith that Peter can
    address it.

    Other than the console work here, there's the usual serial driver
    updates and changes, and a buch of 8250 reworks to try to make that
    driver easier to maintain over time, and have it support more devices
    in the future.

    All of these have been in linux-next for a while"

    * tag 'tty-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (119 commits)
    n_gsm: Drop unneeded cast on netdev_priv
    sc16is7xx: expose RTS inversion in RS-485 mode
    serial: 8250_pci: port failed after wakeup from S3
    earlycon: 8250: Document kernel command line options
    earlycon: 8250: Fix command line regression
    earlycon: Fix __earlycon_table stride
    tty: clean up the tty time logic a bit
    serial: 8250_dw: only get the clock rate in one place
    serial: 8250_dw: remove useless ACPI ID check
    dmaengine: hsu: move memory allocation to GFP_NOWAIT
    dmaengine: hsu: remove redundant pieces of code
    serial: 8250_pci: add Intel Tangier support
    dmaengine: hsu: add Intel Tangier PCI ID
    serial: 8250_pci: replace switch-case by formula for Intel MID
    serial: 8250_pci: replace switch-case by formula
    tty: cpm_uart: replace CONFIG_8xx by CONFIG_CPM1
    serial: jsm: some off by one bugs
    serial: xuartps: Fix check in console_setup().
    serial: xuartps: Get rid of register access macros.
    serial: xuartps: Fix iobase use.
    ...

    Linus Torvalds
     

02 Apr, 2015

1 commit

  • ad80da658   dmaengine: Driver support for FSL RaidEngine device. ... Browse Code »

    The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
    This patch enables the RaidEngine functionality and provides
    hardware offloading capability for memcpy, xor and pq computation.
    It works with async_tx.

    Signed-off-by: Harninder Rai
    Signed-off-by: Xuelin Shi
    Signed-off-by: Vinod Koul

    Xuelin Shi