21 Jul, 2019
1 commit
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Pull more Kbuild updates from Masahiro Yamada:
- match the directory structure of the linux-libc-dev package to that
of Debian-based distributions- fix incorrect include/config/auto.conf generation when Kconfig
creates it along with the .config file- remove misleading $(AS) from documents
- clean up precious tag files by distclean instead of mrproper
- add a new coccinelle patch for devm_platform_ioremap_resource
migration- refactor module-related scripts to read modules.order instead of
$(MODVERDIR)/*.mod files to get the list of created modules- remove MODVERDIR
- update list of header compile-test
- add -fcf-protection=none flag to avoid conflict with the retpoline
flags when CONFIG_RETPOLINE=y- misc cleanups
* tag 'kbuild-v5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (25 commits)
kbuild: add -fcf-protection=none when using retpoline flags
kbuild: update compile-test header list for v5.3-rc1
kbuild: split out *.mod out of {single,multi}-used-m rules
kbuild: remove 'prepare1' target
kbuild: remove the first line of *.mod files
kbuild: create *.mod with full directory path and remove MODVERDIR
kbuild: export_report: read modules.order instead of .tmp_versions/*.mod
kbuild: modpost: read modules.order instead of $(MODVERDIR)/*.mod
kbuild: modsign: read modules.order instead of $(MODVERDIR)/*.mod
kbuild: modinst: read modules.order instead of $(MODVERDIR)/*.mod
scsi: remove pointless $(MODVERDIR)/$(obj)/53c700.ver
kbuild: remove duplication from modules.order in sub-directories
kbuild: get rid of kernel/ prefix from in-tree modules.{order,builtin}
kbuild: do not create empty modules.order in the prepare stage
coccinelle: api: add devm_platform_ioremap_resource script
kbuild: compile-test headers listed in header-test-m as well
kbuild: remove unused hostcc-option
kbuild: remove tag files by distclean instead of mrproper
kbuild: add --hash-style= and --build-id unconditionally
kbuild: get rid of misleading $(AS) from documents
...
17 Jul, 2019
1 commit
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is only generated and included
by drivers/memory/, so it does not need to reside in the globally
visible include/generated/.Signed-off-by: Masahiro Yamada
Acked-by: Santosh Shilimkar
17 Jun, 2019
1 commit
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jedec_ddr_data.c exports 3 symbols, and all of them are only
referenced from drivers/memory/{emif.c,of_memory.c}drivers/memory/ is a better location than lib/.
I removed the Kconfig prompt "JEDEC DDR data" because it is only
select'ed by TI_EMIF, and there is no other user. There is no good
reason in making it a user-configurable CONFIG option.Signed-off-by: Masahiro Yamada
Signed-off-by: Olof Johansson
08 Apr, 2019
1 commit
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drivers/memory/Makefile.asm-offsets is small enough, and included
from a single place.Squash it into drivers/memory/Makefile.
Signed-off-by: Masahiro Yamada
13 Dec, 2018
1 commit
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Add driver for arm pl353 static memory controller. This controller is used in
Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices.Signed-off-by: Naga Sureshkumar Relli
Reviewed-by: Linus Walleij
Signed-off-by: Michal Simek
30 Apr, 2018
1 commit
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Tegra30+ has some minor differences in registers / bits layout compared
to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver
in a preparation for the upcoming MC hot reset controls implementation,
avoiding code duplication.Note that this currently doesn't report the value of MC_GART_ERROR_REQ
because it is located within the GART register area and cannot be safely
accessed from the MC driver (this happens to work only by accident). The
proper solution is to integrate the GART driver with the MC driver, much
like is done for the Tegra SMMU, but that is an invasive change and will
be part of a separate patch series.Signed-off-by: Dmitry Osipenko
Signed-off-by: Thierry Reding
03 Dec, 2017
1 commit
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Certain SoCs like Texas Instruments AM335x and AM437x require parts
of the EMIF PM code to run late in the suspend sequence from SRAM,
such as saving and restoring the EMIF context and placing the memory
into self-refresh.One requirement for these SoCs to suspend and enter its lowest power
mode, called DeepSleep0, is that the PER power domain must be shut off.
Because the EMIF (DDR Controller) resides within this power domain, it
will lose context during a suspend operation, so we must save it so we
can restore once we resume. However, we cannot execute this code from
external memory, as it is not available at this point, so the code must
be executed late in the suspend path from SRAM.This patch introduces a ti-emif-sram driver that includes several
functions written in ARM ASM that are relocatable so the PM SRAM
code can use them. It also allocates a region of writable SRAM to
be used by the code running in the executable region of SRAM to save
and restore the EMIF context. It can export a table containing the
absolute addresses of the available PM functions so that other SRAM
code can branch to them. This code is required for suspend/resume on
AM335x and AM437x to work.In addition to this, to be able to share data structures between C and
the ti-emif-sram-pm assembly code, we can automatically generate all of
the C struct member offsets and sizes as macros by processing
emif-asm-offsets.c into assembly code and then extracting the relevant
data as is done for the generated platform asm-offsets.h files.Acked-by: Tony Lindgren
Acked-by: Russell King
Signed-off-by: Dave Gerlach
Signed-off-by: Santosh Shilimkar
17 Nov, 2017
1 commit
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Pull ARM SoC driver updates from Arnd Bergmann:
"This branch contains platform-related driver updates for ARM and
ARM64, these are the areas that bring the changes:New drivers:
- driver support for Renesas R-Car V3M (R8A77970)
- power management support for Amlogic GX
- a new driver for the Tegra BPMP thermal sensor
- a new bus driver for Technologic Systems NBUS
Changes for subsystems that prefer to merge through arm-soc:
- the usual updates for reset controller drivers from Philipp Zabel,
with five added drivers for SoCs in the arc, meson, socfpa,
uniphier and mediatek families- updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla,
Heiner Kallweit and Lorenzo PieralisiChanges specific to some ARM-based SoC
- the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on
ARM as well- several changes for power management on Broadcom SoCs
- various improvements on Qualcomm, Broadcom, Amlogic, Atmel,
Mediatek- minor Cleanups for Samsung, TI OMAP SoCs"
[ NOTE! This doesn't work without the previous ARM SoC device-tree pull,
because the R8A77970 driver is missing a header file that came from
that pull.The fact that this got merged afterwards only fixes it at this point,
and bisection of that driver will fail if/when you walk into the
history of that driver. - Linus ]* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits)
soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader
bus: add driver for the Technologic Systems NBUS
memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg()
soc: qcom: remove unused label
soc: amlogic: gx pm domain: add PM and OF dependencies
drivers/firmware: psci_checker: Add missing destroy_timer_on_stack()
dt-bindings: power: add amlogic meson power domain bindings
soc: amlogic: add Meson GX VPU Domains driver
soc: qcom: Remote filesystem memory driver
dt-binding: soc: qcom: Add binding for rmtfs memory
of: reserved_mem: Accessor for acquiring reserved_mem
of/platform: Generalize /reserved-memory handling
soc: mediatek: pwrap: fix fatal compiler error
soc: mediatek: pwrap: fix compiler errors
arm64: mediatek: cleanup message for platform selection
soc: Allow test-building of MediaTek drivers
soc: mediatek: place Kconfig for all SoC drivers under menu
soc: mediatek: pwrap: add support for MT7622 SoC
soc: mediatek: pwrap: add common way for setup CS timing extenstion
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap
..
02 Nov, 2017
1 commit
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Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.By default all files without license information are under the default
license of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if
Reviewed-by: Philippe Ombredanne
Reviewed-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
19 Sep, 2017
1 commit
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This driver allows access to DRAM properties, such as the refresh rate,
via the Broadcom STB DDR PHY Front End (DPFE). The refresh rate can be
used as indirect indicator of the DRAM temperature.The driver also allows setting of the sampling interval.
Signed-off-by: Markus Mayer
Signed-off-by: Florian Fainelli
14 Nov, 2016
1 commit
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Create a new driver for the da8xx DDR2/mDDR controller and implement
support for writing to the Peripheral Bus Burst Priority Register.Reviewed-by: Kevin Hilman
Acked-by: Rob Herring
Signed-off-by: Bartosz Golaszewski
[nsekhar@ti.com: subject line adjustment]
Signed-off-by: Sekhar Nori
02 Jun, 2016
1 commit
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The EBI (External Bus Interface) is used to access external peripherals
(NOR, SRAM, NAND, and other specific devices like ethernet controllers).
Each device is assigned a CS line and an address range and can have its
own configuration (timings, access mode, bus width, ...).
This driver provides a generic DT binding to configure a device according
to its requirements.
For specific device controllers (like the NAND one) the SMC timings
should be configured by the controller driver through the matrix and
smc syscon regmaps.Signed-off-by: Boris Brezillon
Signed-off-by: Alexandre Belloni
18 Apr, 2016
1 commit
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This patch adds Exynos SROM controller driver which will handle
save restore of SROM registers during S2R.Signed-off-by: Pankaj Dubey
Reviewed-by: Krzysztof Kozlowski
[p.fedin@samsung.com: tested on SMDK5410]
Tested-by: Pavel Fedin
Signed-off-by: Kukjin Kim
[k.kozlowski: Minor COMPILE_TEST adjustments in Kconfig entries]
Signed-off-by: Krzysztof Kozlowski
25 Feb, 2016
1 commit
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This patch add SMI(Smart Multimedia Interface) driver. This driver
is responsible to enable/disable iommu and control the power domain
and clocks of each local arbiter.Signed-off-by: Yong Wu
Tested-by: Philipp Zabel
Reviewed-by: Daniel Kurtz
Tested-by: Daniel Kurtz
Signed-off-by: Matthias Brugger
Signed-off-by: Joerg Roedel
18 Jul, 2015
1 commit
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This driver makes it possible to configure the static memory
chip selects on the ARM PL172 MultiPort Memory Controller
from a set of properties in DT. Configuration of dynamic
memory is not supported and is left to the boot loader.The intended usage is to setup timing and configuration for
static memory devices like NAND and NOR Flash before they
are probed by a driver.Signed-off-by: Joachim Eastwood
Signed-off-by: Olof Johansson
27 Mar, 2015
1 commit
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Add a driver for the NAND/External Memory Controller (NEMC) on JZ4780
and later SoCs.The primary function of this driver is to configure parameters, such
as timings, for external memory devices using data supplied in the
device tree. Devices connected to the NEMC are represented in the DT
as children of the NEMC node, the driver uses optional properties
specified in these child nodes to configure the parameters of each
bank.Signed-off-by: Alex Smith
Signed-off-by: Zubair Lutfullah Kakakhel
Signed-off-by: Greg Kroah-Hartman
10 Dec, 2014
1 commit
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Pull ARM SoC/OMAP GPMC driver cleanup and move from Arnd Bergmann:
"The GPMC driver has traditionally been considered a part of the OMAP
platform code and tightly interweaved with some of the boards.With this cleanup, it has finally come to the point where it makes
sense to move it out of arch/arm into drivers/memory, where we already
have other drivers for similar hardware. The cleanups are still
ongoing, with the goal of eventually having a standalone driver that
does not require an interface to architecture code.This is a separate branch because of dependencies on multiple other
branches, and to keep the drivers changes separate from the normal
cleanups"* tag 'omap-gpmc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
memory: gpmc: Move omap gpmc code to live under drivers
ARM: OMAP2+: Move GPMC initcall to devices.c
ARM: OMAP2+: Prepare to move GPMC to drivers by platform data header
ARM: OMAP2+: Remove unnecesary include in GPMC driver
ARM: OMAP2+: Drop board file for 3430sdp
ARM: OMAP2+: Drop board file for ti8168evm
ARM: OMAP2+: Drop legacy code for gpmc-smc91x.c
ARM: OMAP2+: Require proper GPMC timings for devices
ARM: OMAP2+: Show bootloader GPMC timings to allow configuring the .dts file
ARM: OMAP2+: Fix support for multiple devices on a GPMC chip select
ARM: OMAP2+: gpmc: Sanity check GPMC fck on probe
ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it
ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices
ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child()
ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()
04 Dec, 2014
1 commit
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The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this driver (via a
custom API or a generic subsystem) to allow clients to register latency
requirements.This driver also registers an IOMMU (SMMU) that's implemented by the
memory controller. It is supported on Tegra30, Tegra114 and Tegra124
currently. Tegra20 has a GART instead.The Tegra SMMU operates on memory clients and SWGROUPs. A memory client
is a unidirectional, special-purpose DMA master. A SWGROUP represents a
set of memory clients that form a logical functional unit corresponding
to a single device. Typically a device has two clients: one client for
read transactions and one client for write transactions, but there are
also devices that have only read clients, but many of them (such as the
display controllers).Because there is no 1:1 relationship between memory clients and devices
the driver keeps a table of memory clients and the SWGROUPs that they
belong to per SoC. Note that this is an exception and due to the fact
that the SMMU is tightly integrated with the rest of the Tegra SoC. The
use of these tables is discouraged in drivers for generic IOMMU devices
such as the ARM SMMU because the same IOMMU could be used in any number
of SoCs and keeping such tables for each SoC would not scale.Acked-by: Joerg Roedel
Signed-off-by: Thierry Reding
29 Nov, 2014
1 commit
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Just move to drivers as further clean-up can now happen there
finally.Let's also add Roger and me to the MAINTAINERS so we get
notified for any patches related to GPMC.Cc: Arnd Bergmann
Acked-by: Roger Quadros
Signed-off-by: Tony Lindgren
25 Aug, 2014
1 commit
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Pull AT91 reset, poweroff and ram drivers from Maxime Ripard:
"This tag holds the various new drivers introduced to move code that used to be
in mach-at91 over to the proper frameworks.These files are the reboot and poweroff code for all AT91 SoCs but the RM9200,
and the ram controller driver is not doing much at the time, except for grabing
the RAM clock in order to leave it always enabled."Conflicts:
arch/arm/mach-at91/Kconfig
30 Jul, 2014
1 commit
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The CoreNet Coherency Fabric is part of the memory subsystem on
some Freescale QorIQ chips. It can report coherency violations (e.g.
due to misusing memory that is mapped noncoherent) as well as
transactions that do not hit any local access window, or which hit a
local access window with an invalid target ID.Signed-off-by: Scott Wood
Reviewed-by: Bharat Bhushan
15 Jul, 2014
1 commit
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Atmel SoCs have one or multiple RAM controllers that need one or multiple clocks
to run.
This driver handle those clocks.Signed-off-by: Alexandre Belloni
Signed-off-by: Maxime Ripard
Acked-by: Nicolas Ferre
01 Mar, 2014
1 commit
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Add new AEMIF driver for EMIF16 Texas Instruments controller.
The EMIF16 module is intended to provide a glue-less interface to
a variety of asynchronous memory devices like ASRA M, NOR and NAND
memory. A total of 256M bytes of any of these memories can be
accessed at any given time via 4 chip selects with 64M byte access
per chip select.Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR
are not supported.This controller is used on SoCs like Davinci, Keysone2
Acked-by: Santosh Shilimkar
Signed-off-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk
Signed-off-by: Greg Kroah-Hartman
19 Feb, 2014
1 commit
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Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall() to make sure this module
has been loaded before MTD partition parsing starts.Signed-off-by: Prabhakar Kushwaha
Acked-by: Arnd Bergmann
Signed-off-by: Greg Kroah-Hartman
22 May, 2013
1 commit
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Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and
Discovery (mv78xx0) supports a Device Bus controller to access several
kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA).This commit adds a driver to handle this controller. So far only
Armada 370, Armada XP and Discovery SoCs are supported.The driver must be registered through a device tree node;
as explained in the binding document.For each child node in the device tree, this driver will:
* set timing parameters
* register a child device
* setup an address decoding window, using the mbus driverKeep in mind the address decoding window setup is only a temporary hack.
This code will be removed from this devbus driver as soon as a proper device
tree binding for the mbus driver is added.Signed-off-by: Ezequiel Garcia
Acked-by: Arnd Bergmann
Acked-by: Jason Cooper
Signed-off-by: Greg Kroah-Hartman
06 Sep, 2012
1 commit
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Commit e6b42eb "memory: emif: add device tree support to emif driver"
added drivers/memory/of_memory.c, which references tables defined in
lib/jedec_ddr_data.c. of_memory.c is compiled when CONFIG_OF, whereas
jedec_ddr_data.c is compiled when CONFIG_DDR. This breaks the build
when CONFIG_OF is defined but not CONFIG_DDR:drivers/built-in.o: In function `of_get_ddr_timings':
drivers/memory/of_memory.c:138: undefined reference to `lpddr2_jedec_timings'
drivers/built-in.o: In function `of_get_min_tck':
drivers/memory/of_memory.c:62: undefined reference to `lpddr2_jedec_min_tck'
make: *** [vmlinux] Error 1To solve this, only compile of_memory.c when CONFIG_OF && CONFIG_DDR,
otherwise, stub out the functions.Signed-off-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman
05 Sep, 2012
1 commit
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Device tree support for the EMIF driver. LPDDR2 generic timings
extraction from device is managed using couple of helper
functions which can be used by other memory controller
drivers.Reviewed-by: Benoit Cousson
Reviewed-by: Grant Likely
Tested-by: Lokesh Vutla
Signed-off-by: Aneesh V
Signed-off-by: Santosh Shilimkar
Cc: Greg Kroah-Hartman
Signed-off-by: Greg Kroah-Hartman
11 May, 2012
2 commits
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Tegra Memory Controller(MC) driver for Tegra30
Added to support MC General interrupts, mainly for IOMMU(SMMU).Signed-off-by: Hiroshi DOYU
Acked-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman -
Tegra Memory Controller(MC) driver for Tegra20
Added to support MC General interrupts, mainly for IOMMU(GART).Signed-off-by: Hiroshi DOYU
Acked-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman
02 May, 2012
1 commit
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EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.Add the basic infrastructure for EMIF driver that includes
driver registration, probe, parsing of platform data etc.Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Tested-by: Lokesh Vutla
Signed-off-by: Greg Kroah-Hartman