05 Sep, 2019

1 commit


31 May, 2019

1 commit

  • Based on 1 normalized pattern(s):

    licensed under the gpl 2

    extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

    has been chosen to replace the boilerplate/reference in 135 file(s).

    Signed-off-by: Thomas Gleixner
    Reviewed-by: Allison Randal
    Reviewed-by: Richard Fontana
    Reviewed-by: Alexios Zavras
    Reviewed-by: Steve Winslow
    Cc: linux-spdx@vger.kernel.org
    Link: https://lkml.kernel.org/r/20190528170026.071193225@linutronix.de
    Signed-off-by: Greg Kroah-Hartman

    Thomas Gleixner
     

31 Oct, 2017

1 commit

  • Take an extra reference to the controller before deregistering it to
    prevent use-after-free in the interrupt handler in case an interrupt
    fires before the line is disabled.

    Fixes: b1353d1c1d45 ("spi: Add Analog Devices AXI SPI Engine controller support")
    Acked-by: Lars-Peter Clausen
    Signed-off-by: Johan Hovold
    Signed-off-by: Mark Brown

    Johan Hovold
     

09 Jan, 2017

1 commit


24 Nov, 2016

1 commit

  • If the driver is built as a module, autoload won't work because the module
    alias information is not filled. So user-space can't match the registered
    device with the corresponding module.

    Export the module alias information using the MODULE_DEVICE_TABLE() macro.

    Before this patch:

    $ modinfo drivers/spi/spi-axi-spi-engine.ko | grep alias
    $

    After this patch:

    $ modinfo drivers/spi/spi-axi-spi-engine.ko | grep alias
    alias: of:N*T*Cadi,axi-spi-engine-1.00.aC*
    alias: of:N*T*Cadi,axi-spi-engine-1.00.a

    Signed-off-by: Javier Martinez Canillas
    Signed-off-by: Mark Brown

    Javier Martinez Canillas
     

26 Apr, 2016

1 commit


06 Feb, 2016

1 commit

  • This patch adds support for the AXI SPI Engine controller which is a FPGA
    soft-peripheral which is used in some of Analog Devices' reference designs.

    The AXI SPI Engine controller is part of the SPI Engine framework[1] and
    allows memory mapped access to the SPI Engine control bus. This allows it
    to be used as a general purpose software driven SPI controller. The SPI
    Engine in addition offers some optional advanced acceleration and
    offloading capabilities, which are not part of this patch though and will
    be introduced separately.

    At the core of the SPI Engine framework is a small sort of co-processor
    that accepts a command stream and turns the commands into low-level SPI
    transactions. Communication is done through three memory mapped FIFOs in
    the register map of the AXI SPI Engine peripheral. One FIFO for the command
    stream and one each for transmit and receive data.

    The driver translates a spi_message in a command stream and writes it to
    the peripheral which executes it asynchronously. This allows it to perform
    very precise timings which are required for some SPI slave devices to
    achieve maximum performance (e.g. analog-to-digital and digital-to-analog
    converters). The execution flow is synchronized to the host system by a
    special synchronize instruction which generates a interrupt.

    [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine

    Signed-off-by: Lars-Peter Clausen
    Signed-off-by: Mark Brown

    Lars-Peter Clausen