29 Jul, 2019
1 commit
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Implement program support.
Restruct code to check hole/ecc region.
Use ATF SIP to program fuse
Add mutex lock to protect accessSigned-off-by: Peng Fan
Reviewed-by: Ye Li
25 Jul, 2019
1 commit
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Remove clocks that dont exist in imx8qxp.
Change clock names to match HW.Signed-off-by: Ranjani Vaidyanathan
11 Jul, 2019
1 commit
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Fix build break, this file was missed when adding xen 4.19 support.
Signed-off-by: Peng Fan
31 May, 2019
1 commit
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Instead of just raising irq0 for all the cores, we mask the irq0 for all the
non-target cores, this way waking up only the core we want. All of this
is done now in TF-A.Also, since this new workaround doesn't need the IOMUX_GPR1 register here
in kernel, the IOMUX_GPR reg entry inside the gic dts node can be removed.In order for this to work, the following commit is needed in TF-A:
0e91ff59720d0756 ("MLK-21399 plat: imx8mq: gpc: Workaround for ERR11171")Signed-off-by: Abel Vesa
Reviewed-by: Leonard Crestez
18 Apr, 2019
13 commits
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This patch updates SCFW API to v1.7, based on below commit:
252281d48647 ("SCF-105: Update wiki.")
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
(cherry picked from commit d62625563213b516c6238e970f31d07d20bbe19e) -
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.(2): 400mts, the DDRC core clock is source from sys1_pll_400m,
the DDRC apb clock is is sourced from sys1_pll_40m.(3): 100mts, the DDRC core clock is sourced from sys1_pll_100m,
the DDRC apb clock is sourced from sys1_pll_40m.In our busfreq driver, we have three mode supported:
* high bus mode 3200mts;
* audio bus mode 400mts;
* low bus mode 100mts;The actual DDR frequency is done in ARM trusted firmware by calling
the SMCC SiP service call.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang(cherry picked from commit 60a2002f752404b5fc30b374bc71a3975902eb7a)
Use CONFIG_HAVE_IMX_BUSFREQ instead of just CONFIG_ARCH_FSL_IMX8MQ
Signed-off-by: Leonard Crestez -
This watchdog driver is a virtual driver in Linux and call ATF interface
where call SCFW eventually. In SCFW, it's done by SCU timer tick instead
of hardware watchdog.This is why we have to call ATF because such system
resource owned by secure patition.Currently, booard reset happen if not
ping this software watchdog in time in linux side, may change to partition
reboot once SCFW support this feature in the future.
BuildInfo:
- SCFW 93c142a9, IMX-MKIMAGE 2522fd70, ATF f2547fb
- U-Boot 2017.03-00097-gd7599cfSigned-off-by: Robin Gong
Reviewed-by: Anson Huang
(cherry picked from commit 3582decf35940566ed5eb43393c422315931f183) -
Enable i.MX8 SCU notifier for handling general MU
irq event.Signed-off-by: Anson Huang
-
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Peng Fan
Signed-off-by: Leonard Crestez -
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Bai Ping
Signed-off-by: Anson Huang
Signed-off-by: Peng Fan
Signed-off-by: Leonard Crestez -
This is enabled via CONFIG_HAVE_IMX_SC
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
This was changed at some point by SC firmware but imx linux releases
didn't pick up the change and some drivers don't even compile with a
16-bit sc_rsrc_t.Fix by overwriting SC API with imx_4.14 definition.
Signed-off-by: Leonard Crestez
-
Uses same layout as imx_4.14.y
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
This file contains many defines for SIP calls to imx ATF.
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Leonard Crestez
-
If support for imx_src_is_m4_enabled is not compiled then just return
the default value "false".Signed-off-by: Leonard Crestez
-
As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.Signed-off-by: Anson Huang
Also made SOC_IMX6SX select IMX_SEMA4 as part of this commit to fix
build failures.Signed-off-by: Leonard Crestez
[Arul: fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel
28 Sep, 2018
1 commit
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Add a couple of new APIs to check the probing status of qman and bman:
'int bman_is_probed()' and 'int qman_is_probed()'.
They return the following values.
* 1 if qman/bman were probed correctly
* 0 if qman/bman were not yet probed
* -1 if probing of qman/bman failed
Drivers that use qman/bman driver services are required to use these
APIs before calling any functions exported by qman or bman drivers
or otherwise they will crash the kernel.
The APIs will be used in the following couple of qbman portal patches
and later in the series in the dpaa1 ethernet driver.Signed-off-by: Laurentiu Tudor
Signed-off-by: Li Yang
26 Jul, 2018
2 commits
-
…o/linux into next/drivers
Various updates to soc/fsl for 4.19
Moves DPAA2 DPIO driver from staging to fsl/soc
Adds multiple-pin support to QE gpio driver* tag 'soc-fsl-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: cleanup Kconfig menu
soc: fsl: dpio: Convert DPIO documentation to .rst
staging: fsl-mc: Remove remaining files
staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
staging: fsl-dpaa2: eth: move generic FD defines to DPIO
soc: fsl: qe: gpio: Add qe_gpio_set_multipleSigned-off-by: Olof Johansson <olof@lixom.net>
-
…it/agross/linux into next/drivers
Qualcomm ARM Based Driver Updates for v4.19
* Add Qualcomm LLCC driver
* Add Qualcomm RPMH controller
* Fix memleak in Qualcomm RMTFS
* Add dummy qcom_scm_assign_mem()
* Fix check for global partition in SMEM* tag 'qcom-drivers-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
soc: qcom: rmtfs-mem: fix memleak in probe error paths
soc: qcom: llc-slice: Add missing MODULE_LICENSE()
drivers: qcom: rpmh: fix unwanted error check for get_tcs_of_type()
drivers: qcom: rpmh-rsc: fix the loop index check in get_req_from_tcs
firmware: qcom: scm: add a dummy qcom_scm_assign_mem()
drivers: qcom: rpmh-rsc: Check cmd_db_ready() to help children
drivers: qcom: rpmh-rsc: allow active requests from wake TCS
drivers: qcom: rpmh: add support for batch RPMH request
drivers: qcom: rpmh: allow requests to be sent asynchronously
drivers: qcom: rpmh: cache sleep/wake state requests
drivers: qcom: rpmh-rsc: allow invalidation of sleep/wake TCS
drivers: qcom: rpmh-rsc: write sleep/wake requests to TCS
drivers: qcom: rpmh: add RPMH helper functions
drivers: qcom: rpmh-rsc: log RPMH requests in FTRACE
dt-bindings: introduce RPMH RSC bindings for Qualcomm SoCs
drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs
drivers: soc: Add LLCC driver
dt-bindings: Documentation for qcom, llcc
soc: qcom: smem: Correct check for global partitionSigned-off-by: Olof Johansson <olof@lixom.net>
25 Jul, 2018
1 commit
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Move the NXP DPIO (Datapath I/O Driver) out of the
drivers/staging directory and into the drivers/soc/fsl directory.The DPIO driver enables access to Queue and Buffer Manager (QBMAN)
hardware on NXP DPAA2 devices. This is a prerequisite to moving the
DPAA2 Ethernet driver out of staging.Signed-off-by: Roy Pledge
Reviewed-by: Horia Geantă
Reviewed-by: Ioana Radulescu
Signed-off-by: Li Yang
22 Jul, 2018
5 commits
-
Platform drivers need make a lot of resource state requests at the same
time, say, at the start or end of an usecase. It can be quite
inefficient to send each request separately. Instead they can give the
RPMH library a batch of requests to be sent and wait on the whole
transaction to be complete.rpmh_write_batch() is a blocking call that can be used to send multiple
RPMH command sets. Each RPMH command set is set asynchronously and the
API blocks until all the command sets are complete and receive their
tx_done callbacks.Signed-off-by: Lina Iyer
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Matthias Kaehlcke
Signed-off-by: Andy Gross -
Platform drivers that want to send a request but do not want to block
until the RPMH request completes have now a new API -
rpmh_write_async().The API allocates memory and send the requests and returns the control
back to the platform driver. The tx_done callback from the controller is
handled in the context of the controller's thread and frees the
allocated memory. This API allows RPMH requests from atomic contexts as
well.Signed-off-by: Lina Iyer
Signed-off-by: Raju P.L.S.S.S.N
Signed-off-by: Andy Gross -
Active state requests are sent immediately to the RSC controller, while
sleep and wake state requests are cached in this driver to avoid taxing
the RSC controller repeatedly. The cached values will be sent to the
controller when the rpmh_flush() is called.Generally, flushing is a system PM activity and may be called from the
system PM drivers when the system is entering suspend or deeper sleep
modes during cpuidle.Also allow invalidating the cached requests, so they may be re-populated
again.Signed-off-by: Lina Iyer
[rplsssn: remove unneeded semicolon, address line over 80chars error]
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Evan Green
Reviewed-by: Matthias Kaehlcke
Signed-off-by: Andy Gross -
Sending RPMH requests and waiting for response from the controller
through a callback is common functionality across all platform drivers.
To simplify drivers, add a library functions to create RPMH client and
send resource state requests.rpmh_write() is a synchronous blocking call that can be used to send
active state requests.Signed-off-by: Lina Iyer
Signed-off-by: Raju P.L.S.S.S.N
Signed-off-by: Andy Gross -
Add controller driver for QCOM SoCs that have hardware based shared
resource management. The hardware IP known as RSC (Resource State
Coordinator) houses multiple Direct Resource Voter (DRV) for different
execution levels. A DRV is a unique voter on the state of a shared
resource. A Trigger Control Set (TCS) is a bunch of slots that can house
multiple resource state requests, that when triggered will issue those
requests through an internal bus to the Resource Power Manager Hardened
(RPMH) blocks. These hardware blocks are capable of adjusting clocks,
voltages, etc. The resource state request from a DRV are aggregated
along with state requests from other processors in the SoC and the
aggregate value is applied on the resource.Some important aspects of the RPMH communication -
- Requests are with some header information
- Multiple requests (upto 16) may be sent through a TCS, at a time
- Requests in a TCS are sent in sequence
- Requests may be fire-n-forget or completion (response expected)
- Multiple TCS from the same DRV may be triggered simultaneously
- Cannot send a request if another request for the same addr is in
progress from the same DRV
- When all the requests from a TCS are complete, an IRQ is raised
- The IRQ handler needs to clear the TCS before it is available for
reuse
- TCS configuration is specific to a DRV
- Platform drivers may use DRV from different RSCs to make requestsResource state requests made when CPUs are active are called 'active'
state requests. Requests made when all the CPUs are powered down (idle
state) are called 'sleep' state requests. They are matched by a
corresponding 'wake' state requests which puts the resources back in to
previously requested active state before resuming any CPU. TCSes are
dedicated for each type of requests. Active mode TCSes (AMC) are used to
send requests immediately to the resource, while control TCS are used to
provide specific information to the controller. Sleep and Wake TCS send
sleep and wake requests, after and before the system halt respectively.Signed-off-by: Lina Iyer
Signed-off-by: Raju P.L.S.S.S.N
Signed-off-by: Andy Gross
22 Jun, 2018
1 commit
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Recent Raspberry Pi firmware provides a mailbox property to detect
under-voltage conditions. Here is the current definition.The u32 value returned by the firmware is divided into 2 parts:
- lower 16-bits are the live value
- upper 16-bits are the history or sticky valueBits:
0: undervoltage
1: arm frequency capped
2: currently throttled
16: undervoltage has occurred
17: arm frequency capped has occurred
18: throttling has occurredSigned-off-by: Stefan Wahren
Signed-off-by: Eric Anholt
Reviewed-by: Eric Anholt
12 Jun, 2018
1 commit
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Pull ARM SoC late updates from Olof Johansson:
"This is a branch with a few merge requests that either came in late,
or took a while longer for us to review and merge than usual and thus
cut it a bit close to the merge window. We stage them in a separate
branch and if things look good, we still send them up -- and that's
the case here.This is mostly DT additions for Renesas platforms, adding IP block
descriptions for existing and new SoCs.There are also some driver updates for Qualcomm platforms for SMEM/QMI
and GENI, which is their generalized serial protocol interface"* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits)
soc: qcom: smem: introduce qcom_smem_virt_to_phys()
soc: qcom: qmi: fix a buffer sizing bug
MAINTAINERS: Update pattern for qcom_scm
soc: Unconditionally include qcom Makefile
soc: qcom: smem: check sooner in qcom_smem_set_global_partition()
soc: qcom: smem: fix qcom_smem_set_global_partition()
soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private()
soc: qcom: smem: byte swap values properly
soc: qcom: smem: return proper type for cached entry functions
soc: qcom: smem: fix first cache entry calculation
soc: qcom: cmd-db: Make endian-agnostic
drivers: qcom: add command DB driver
arm64: dts: renesas: salvator-common: Add ADV7482 support
ARM: dts: r8a7740: Add CEU1
ARM: dts: r8a7740: Add CEU0
arm64: dts: renesas: salvator-common: enable VIN
arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7795-es1: add CSI-2 node
...
02 Jun, 2018
1 commit
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The tegra_cpuidle_pcie_irqs_in_use() function is stubbed out for non-ARM
builds, but now we can compile-test the Tegra pci driver on non-Tegra
ARM platforms as well, which results in a new link error:drivers/pci/host/pci-tegra.o: In function `tegra_pcie_map_irq':
pci-tegra.c:(.text+0x288): undefined reference to `tegra_cpuidle_pcie_irqs_in_use'
drivers/pci/host/pci-tegra.o: In function `tegra_msi_map':
pci-tegra.c:(.text+0xba0): undefined reference to `tegra_cpuidle_pcie_irqs_in_use'This adapts the #ifdef statement to match the exact condition under which
the function can be called.Fixes: 51bc085d6454 ("PCI: Improve host drivers compile test coverage")
Cc: Rob Herring
Cc: Lorenzo Pieralisi
Signed-off-by: Arnd Bergmann
Acked-by: Rob Herring
Acked-by: Thierry Reding
Signed-off-by: Olof Johansson
27 May, 2018
1 commit
-
…it/agross/linux into next/late
Qualcomm ARM Based Driver Updates for v4.18
* Various SMEM updates/fixes
* Add qcom_smem_virt_to_phys SMEM API
* Update MAINTAINERS to include qcom_scm pattern
* Add Qualcomm Command DB driver
* Add Qualcomm SCM compatible for IPQ4019
* Add MSM8998 to smd-rpm compatible list
* Add Qualcomm GENI based QUP wrapper
* Fix Qualcomm QMI buffer sizing bug* tag 'qcom-drivers-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
soc: qcom: smem: introduce qcom_smem_virt_to_phys()
soc: qcom: qmi: fix a buffer sizing bug
MAINTAINERS: Update pattern for qcom_scm
soc: Unconditionally include qcom Makefile
soc: qcom: smem: check sooner in qcom_smem_set_global_partition()
soc: qcom: smem: fix qcom_smem_set_global_partition()
soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private()
soc: qcom: smem: byte swap values properly
soc: qcom: smem: return proper type for cached entry functions
soc: qcom: smem: fix first cache entry calculation
soc: qcom: cmd-db: Make endian-agnostic
drivers: qcom: add command DB driver
soc: qcom: Add GENI based QUP Wrapper driver
soc: qcom: smd-rpm: Add msm8998 compatible
firmware: qcom: scm: Add ipq4019 soc compatibleSigned-off-by: Olof Johansson <olof@lixom.net>
26 May, 2018
1 commit
-
Command DB is a simple database in the shared memory of QCOM SoCs, that
provides information regarding shared resources. Some shared resources
in the SoC have properties that are probed dynamically at boot by the
remote processor. The information pertaining to the SoC and the platform
are made available in the shared memory. Drivers can query this
information using predefined strings.Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by: Bjorn Andersson
Reviewed-by: Stephen Boyd
Signed-off-by: Andy Gross
25 May, 2018
1 commit
-
…l/git/tegra/linux into next/drivers
memory: tegra: Changes for v4.18-rc1
This contains some cleanup of the memory controller driver as well as
unification work to share more code between Tegra20 and later SoC
generations. Also included are an implementation for the hot resets
functionality by the memory controller which is required to properly
reset busy hardware.* tag 'tegra-for-4.18-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions
memory: tegra: Remove Tegra114 SATA and AFI reset definitions
memory: tegra: Register SMMU after MC driver became ready
memory: tegra: Add Tegra210 memory controller hot resets
memory: tegra: Add Tegra124 memory controller hot resets
memory: tegra: Add Tegra114 memory controller hot resets
memory: tegra: Add Tegra30 memory controller hot resets
memory: tegra: Add Tegra20 memory controller hot resets
memory: tegra: Introduce memory client hot reset
memory: tegra: Squash tegra20-mc into common tegra-mc driver
memory: tegra: Remove unused headers inclusions
memory: tegra: Apply interrupts mask per SoC
memory: tegra: Setup interrupts mask before requesting IRQ
memory: tegra: Do not handle spurious interrupts
dt-bindings: memory: tegra: Add hot resets definitionsSigned-off-by: Olof Johansson <olof@lixom.net>
30 Apr, 2018
2 commits
-
In order to reset busy HW properly, memory controller needs to be
involved, otherwise it is possible to get corrupted memory or hang machine
if HW was reset during DMA. Introduce memory client 'hot reset' that will
be used for resetting of busy HW.Signed-off-by: Dmitry Osipenko
Signed-off-by: Thierry Reding -
Tegra30+ has some minor differences in registers / bits layout compared
to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver
in a preparation for the upcoming MC hot reset controls implementation,
avoiding code duplication.Note that this currently doesn't report the value of MC_GART_ERROR_REQ
because it is located within the GART register area and cannot be safely
accessed from the MC driver (this happens to work only by accident). The
proper solution is to integrate the GART driver with the MC driver, much
like is done for the Tegra SMMU, but that is an invasive change and will
be part of a separate patch series.Signed-off-by: Dmitry Osipenko
Signed-off-by: Thierry Reding
27 Apr, 2018
1 commit
-
Currently we are enabling handling of interrupts specific to Tegra124+
which happen to overlap with previous generations. Let's specify
interrupts mask per SoC generation for consistency and in a preparation
of squashing of Tegra20 driver into the common one that will enable
handling of GART faults which may be undesirable by newer generations.Signed-off-by: Dmitry Osipenko
Signed-off-by: Thierry Reding
17 Apr, 2018
1 commit
-
If CONFIG_RASPBERRYPI_FIRMWARE=n:
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_polarity’:
drivers/gpio/gpio-raspberrypi-exp.c:71: warning: ‘get.polarity’ is used uninitialized in this function
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_direction’:
drivers/gpio/gpio-raspberrypi-exp.c:150: warning: ‘get.direction’ is used uninitialized in this functionThe dummy firmware interface functions return 0, which means success,
causing subsequent code to make use of the never initialized output
parameter.Fix this by making the dummy functions return an error code (-ENOSYS)
instead.Note that this assumes the firmware always fills in the requested data
in the CONFIG_RASPBERRYPI_FIRMWARE=y case.Fixes: d45f1a563b92dac7 ("staging: vc04_services: fix up rpi firmware functions")
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Eric Anholt
Signed-off-by: Florian Fainelli
06 Apr, 2018
1 commit
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Pull ARM SoC driver updates from Arnd Bergmann:
"The main addition this time around is the new ARM "SCMI" framework,
which is the latest in a series of standards coming from ARM to do
power management in a platform independent way.This has been through many review cycles, and it relies on a rather
interesting way of using the mailbox subsystem, but in the end I
agreed that Sudeep's version was the best we could do after all.Other changes include:
- the ARM CCN driver is moved out of drivers/bus into drivers/perf,
which makes more sense. Similarly, the performance monitoring
portion of the CCI driver are moved the same way and cleaned up a
little more.- a series of updates to the SCPI framework
- support for the Mediatek mt7623a SoC in drivers/soc
- support for additional NVIDIA Tegra hardware in drivers/soc
- a new reset driver for Socionext Uniphier
- lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
drivers/firmware and drivers/reset across platforms"* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
reset: uniphier: add ethernet reset control support for PXs3
reset: stm32mp1: Enable stm32mp1 reset driver
dt-bindings: reset: add STM32MP1 resets
reset: uniphier: add Pro4/Pro5/PXs2 audio systems reset control
reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency
reset: modify the way reset lookup works for board files
reset: add support for non-DT systems
clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_remove
firmware: arm_scmi: prevent accessing rate_discrete uninitialized
hwmon: (scmi) return -EINVAL when sensor information is unavailable
amlogic: meson-gx-socinfo: Update soc ids
soc/tegra: pmc: Use the new reset APIs to manage reset controllers
soc: mediatek: update power domain data of MT2712
dt-bindings: soc: update MT2712 power dt-bindings
cpufreq: scmi: add thermal dependency
soc: mediatek: fix the mistaken pointer accessed when subdomains are added
soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC
soc: mediatek: avoid hardcoded value with bus_prot_mask
dt-bindings: soc: add header files required for MT7623A SCPSYS dt-binding
dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC
...
27 Mar, 2018
1 commit
-
…ernel/git/tegra/linux into next/drivers
Pull "firmware: Changes for v4.17-rc1" from Thierry Reding:
These changes are rather small, with just a fix for a return value check
and some preparatory work for Tegra194 BPMP support.* tag 'tegra-for-4.17-firmware' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
firmware: tegra: adjust tested variable
firmware: tegra: Simplify channel management
19 Mar, 2018
1 commit
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Linux 4.16-rc5 merged into the GPIO devel branch to resolve
a nasty conflict between fixes and devel in the RCAR driver.Signed-off-by: Linus Walleij
08 Mar, 2018
1 commit
-
The Tegra194 BPMP only implements 5 channels (4 to BPMP, 1 to CCPLEX),
and they are not placed contiguously in memory. The current channel
management in the BPMP driver does not support this.Simplify and refactor the channel management such that only one atomic
transmit channel and one receive channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
