Eric Lee / smarc-fsl-linux-kernel

11 Mar, 2016

1 commit

16 Feb, 2016

2 commits

  • e9dd4edcc   spi: bcm2835aux: fix CPOL/CPHA setting ... Browse Code »

    The auxiliary spi supports only CPHA=0 modes as the first bit is
    always output to the pin before the first clock cycle. In CPHA=1
    modes the first clock edge outputs the second bit hence the slave
    can never read the first bit.

    Also the CPHA registers switch between clocking data in/out on
    rising/falling edge hence depend on the CPOL setting.

    Signed-off-by: Stephan Olbrich
    Reviewed-by: Eric Anholt
    Signed-off-by: Mark Brown

    Stephan Olbrich
     
  • b4e2adef6   spi: bcm2835aux: set up spi-mode before asserting cs-gpio ... Browse Code »

    When using reverse polarity for clock (spi-cpol) on a device
    the clock line gets altered after chip-select has been asserted
    resulting in an additional clock beat, which confuses hardware.

    This happens due to the fact, the the hardware was initialized
    and reset at the begin and end of each transfer which results
    in default state for all lines except chip-select which is
    handled by the spi-subsystem as gpio-cs is used.

    To avoid this situation this patch moves the setup of polarity
    (spi-cpol and spi-cpha) outside of the chip-select into
    prepare_message, which is run prior to asserting chip-select.

    Signed-off-by: Stephan Olbrich
    Reviewed-by: Martin Sperl
    Tested-by: Martin Sperl
    Reviewed-by: Eric Anholt
    Signed-off-by: Mark Brown

    Stephan Olbrich
     

11 Feb, 2016

1 commit

10 Feb, 2016

1 commit

16 Oct, 2015

2 commits

  • 07bce09e1   spi: bcm2835aux: change initialization order and switch to platform_get_irq ... Browse Code »

    Change the initialization order of the HW so that the interrupt
    is only requested after the HW is initialized

    Also the use of irq_of_parse_and_map is replaced by platform_get_irq.

    Signed-off-by: Martin Sperl
    Signed-off-by: Mark Brown

    Martin Sperl
     
  • 72aac02b3   spi: bcm2835aux: fixed bad data on longer transfers ... Browse Code »

    There are strange issues with the auxiliary spi device that result
    in "lost" data in the RX path if the fifo is filled by too much
    (even though the status register is checked if new data can get filled
    in).

    This has been observed primarily for the interrupt case.
    Polling works fine, probably because the RX fifo is pulled immediately
    when in the tight polling loop.

    For that reason we have to limit the pending bytes to less than 15
    when filling the fifo in interrupt mode.

    There also was an issue returning the "wrong" last 1/2 bytes
    of a transfer when the transfer is not a multiple of 3 bytes.
    (this impacted polling and interrupt modes)

    Also fixed an overflow in the estimation of the transfer time used
    to decide if we run in interrupt or polling mode (found with the
    spi-bcm2835.c driver originally).

    Reported-by: Georgii Staroselskii
    Signed-off-by: Martin Sperl
    Signed-off-by: Mark Brown

    Martin Sperl
     

07 Oct, 2015

1 commit

  • 1ea29b39f   spi: bcm2835aux: add bcm2835 auxiliary spi device driver ... Browse Code »

    The bcm2835 has 2 auxiliary spi bus masters spi1 and spi2.

    This implements the driver to enable these devices.

    The driver does not implement native chip-selects but uses
    the aribtrary GPIO-chip-selects provided by the spi-chipselect.

    Note that this driver relies on the fact that
    the clock is implemented by the clk-bcm2835-aux driver,
    which enables/disables the HW block when requesting/releasing
    the clock.

    Signed-off-by: Martin Sperl
    Acked-by: Eric Anholt
    Signed-off-by: Mark Brown

    Martin Sperl