12 Apr, 2018
1 commit
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The microphone only connect to left input, when record stereo channel
data, the right channel is mute. Add 'ADC Data Output Select' mixer
control that user can select the wanted configure. The default setting
is 'Left Data = Left ADC; Right Data = Left ADC'.Signed-off-by: Shengjiu Wang
(cherry picked from commit cce63c3e843b7d705df6e36adffc0226bfe40e42)
21 Mar, 2018
39 commits
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The FB_MX8_HDMI is removed, the dependency is changed
to DRM_IMX_HDP.Signed-off-by: Shengjiu Wang
Reviewed-by: Sandor Yu -
Fix bug when PDN gpio is requested instead of mute gpio.
Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Daniel Baluta -
For some cases (like AMIX) pinctrl may be null - this
breaks SAI functionality. Enforce pinctrl null pointer
checking prior calling any function which involves
pins state changes.Signed-off-by: Viorel Suman
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Replace DSD related code with calls to DSD helper functions.
Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com -
Add DSD utilities helper.
Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com -
Using TDM256 mode (our only supported mode) in order to
support 192KHz we would need a MCLK of 192000 * 512 = 98304000.But maximum frequency supported by the Audio PLL is 4.91 MHz.
Reviewed-by: Shengjiu Wang
Signed-off-by: Daniel Baluta -
In order for TDM to correctly work we need that MCLK and
BCLK to follow the values in Table 9.Thus,
* TDM128: BCLK = 128fs, MCLK = 128-1024fs
* TDM256: BCLK = 256fs, MCLK = 256-1024fs
* TDM512: BCLK = 512fs, MCLK = 512-1024fsWe assume only support TDM256 for the moment.
Reviewed-by: Shengjiu Wang
Signed-off-by: Daniel Baluta -
We cannot both derive SAI BCLK for 384KHz-S32/768KHz-S16 and
respect the codec MCLK restrictions shown in AK4458 datasheet
Table 5, 6 and 7.
Since we can have same master clock for SAI and Codec in Manual
Mode, we've chosen to use it instead of Auto Mode.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Shengjiu Wang -
Transmit data pins will output zero when slots are masked or channels
are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when
slots are masked or channels are disabled. When data pins are tri-stated,
there is noise on some channels when FS clock value is high and data is
read while fsclk is transitioning from high to low.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Shengjiu Wang -
use the rpmsg_wm8960 codec instead of the dummy codec
Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
Receive message is only used when the type is B. originally
we copy the receive message to revg_msg all the time, when
the message type is C, which will overide the revg_msg, which
cause the get codec data command return wrong value.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
register rpmsg codec after the rpmsg-audio-channel is
ready.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
This codec is accessed by rpmsg. As the wm8960 is controlled
mainly by M4, so we only add volume in this rpmsg_wm8960 codec.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
rpmsg provide command for A7 side to set the codec value and get
codec value by i2c. In this case, the A7 can control the codec.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
ULP B0 integrate the latest SAI IP, there is version id and
parameter id register in the beginning, so update the offset
for ULP B0Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
With the current multipliers SAI isn't able to derive a correct bitclk.
e.g: When playing at 786Khz with current multiplier
MCLK = 22579200, requested freq 22579200 but SAI wants:
MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution
is to add a 2x factor to mclk.Signed-off-by: Viorel Suman
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With the current multipliers SAI isn't able to derive a correct bitclk.
e.g: When recording at 786Khz with current multiplier
MCLK = 24576000, requested freq 24576000 but SAI wants:
MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution
is to add a 2x factor to mclk.Reviewed-by: Viorel Suman
Signed-off-by: Daniel Baluta -
switch to generic hdmi codec, which provide the api for get
the edid information.
Add snd controls which is the interface for user to query
the HDMI capibility. ( channels, rates, formats)Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman -
MCLK frequency is determined based on LRCK frequency, according
to the operation mode. Because AK5558 runs in Auto Mode, we use
table 5 from datasheet to set the correct MCLK.Multiplier must be set twice as value shown in RM because SAI
MCLK must be at least double the BCLK.Signed-off-by: Daniel Baluta
Reviewed-by: Cosmin Samoila -
"
commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5
Author: Chuck Cannon
Date: Tue Feb 6 08:54:16 2018 -0600Add unique ID API call. Required to get info needed for SECO fus
programming. Added info command to DM.
"Signed-off-by: Ranjani Vaidyanathan
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According to AK4458 RM the MCLK freq need to be set
externaly as function of LRCK frequency. Notice that
multiplier is twice the value shown in RM since SAI
MCLK must be at least double the BCLK.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Viorel Suman -
According to AK4497 RM the MCLK freq need to be set
externaly as function of LRCK frequency.Signed-off-by: Viorel Suman
Suggested-by: Shengjiu Wang
Reviewed-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
Set the requested clock rate in "set_sysclk" for specified clock id.
Signed-off-by: Viorel Suman
Suggested-by: Shengjiu Wang
Reviewed-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
The current implementation suggest that MAST1 frequency is to be changed,
which is wrong. Use FSL_SAI_CLK_BIT clock id instead of FSL_SAI_CLK_MAST1
in order to make the code more intuitive and to signal proper
clk_id to SAI.Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
Introduce FSL_SAI_CLK_BIT clock id in order to distinguish
the bit clock and master clocks in "set_sysclk" API.Signed-off-by: Viorel Suman
Suggested-by: Shengjiu Wang
Reviewed-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
The register definition is not completed for SAI support
8 transmit data register and 8 receive data register.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
There is two ak4458 codecs which share some pdn gpio. If assign
the pdn gpio to one codec, will cause the another codec error:ak4458 1-0012: Unable to sync registers 0x0-0x0. -6
The reason is that if the codec driver is trying to do regcache_sync,
but another codec is resetting the pdn gpio in same time, the
regcache_sync will fail.So Move the pdn gpio to machine driver, machine driver will
control this gpio for two codecs.Signed-off-by: Shengjiu Wang
Reviewed-by: Cosmin Samoila -
There is ak4458 audio card even no audio board connected, which
is caused by there is no error return value even the i2c access
failed.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
The "snd_pcm_hw_constraint_minmax" call may return a positive
non-error integer so that the subsequent "snd_pcm_hw_constraint_mask64"
call is never invoked, thus the formats are never enforced.
Fix the error handling so that only negative results are considered.Signed-off-by: Viorel Suman
Reviewed-by: Daniel Baluta -
Because fsl_sai_dai rates doesn't have a specific set of
rate values (.rates = SNDRV_PCM_RATE_KNOT) we need to provide
rate_min and rate_max otherwise functions trying to get
supported parameters will get confused and return an error.Fixes: 1b6f0496e013 ("MLK-17428-8: ASoC: fsl_sai: support 768KHz sample rate")
Reviewed-by: Viorel Suman
Signed-off-by: Daniel Baluta -
With commit 69201427e188 ("MLK-17470: ASoC: ak4497: automatically select dsdsel
in driver") the "ak4497_priv.nDSDSel" field might not reflect the real dsdsel
option. In order to simplify the approach and avoid future inconsistencies the
field is removed and dsdsel option is read/stored directly to/from codec
registers. Aside of this a missing dsdsel option for 22.5792MHz is introduced
in "ak4497_set_dsdsel" method, now this method being fully compatible with
commit 69201427e188 ("MLK-17470: ASoC: ak4497: automatically select dsdsel in
driver").Signed-off-by: Viorel Suman
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When in TDM mode, change constraints for rate and allow only
rates in [8KHz, 96KHz] due to the limitations of SAI master
clock. If rate is higher than 96KHz, the TX rate cannot be
obtained using only a 49MHz SAI clock.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Daniel Baluta -
In normal mode we need to test SAI capability of supporting
higher rates so adjust constraints list to allow 384KHz
and 768KHz.Signed-off-by: Daniel Baluta
Reviewed-by: Shengjiu Wang -
Add 384KHz and 768KHz as supported rates and add
different constraints for number of channels when
in tdm mode.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Shengjiu Wang -
TDM mode is enabled when "fsl,tdm" property is added in machine
driver dts node. When using TDM mode, SND_SOC_DAIFMT_DSP_B format
is used and the tdm slot_width is set to 32.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Shengjiu Wang -
Based on slot_width and params_width, we will set
the format and TDM mode as specified in AK4458
datasheet.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Shengjiu Wang -
sound/soc/fsl/imx-wm8962.c: In function ‘imx_wm8962_probe’:
sound/soc/fsl/imx-wm8962.c:810:2: warning: ‘cpu_np’ may be used uninitialized in this function [-Wmaybe-uninitialized]
of_node_put(cpu_np);
^~~~~~~~~~~~~~~~~~~Signed-off-by: Shengjiu Wang
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With the existing implementation the SAI pinctrl state is restored to
default after resume - this breaks DSD playback after resume.
Restore DSD pinctrl state in snd_soc_dai_driver resume callback.Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang -
add fsl,tdm property, in tdm mode, the slot_width is fixed to
32 bit.Signed-off-by: Shengjiu Wang
