01 Nov, 2019
1 commit
18 Mar, 2019
1 commit
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Remove the quirk for disable cyw4356 D3 mode since current FW
already support it.
This revert the commit 28db0ac248b3("MLK-20716 PCI: add quirk for
cyw4356 to disable D3 mode")Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
12 Feb, 2019
38 commits
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Add quirk for cyw4356 to disable D3 mode because current firmware
still doesn't support D3 mode.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
MSI is broken on CYW4356/4359 chips. This causes CYW4356 1CX not
work on i.MX8x platforms with bandwidth test. It is known issue
that i.MX8x PCIe host driver MSI interrupt lost.Disable MSI completely for this chipset to let wifi can stable work
until PCIe RC driver fix the issue.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
- replace the sleep by the udelay, since it would be used
in the no_irq_suspend/resume callbacks.
- aligned the retries to the PHY_PLL_LOCK_WAIT_MAX_RETRIESSigned-off-by: Richard Zhu
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Use the external osc as the pcie refclk on 8mm evk board.
- Do not turn off the over ride of rc's clkreq#, when
L1SS is not enabled.
NOTE: L1SS_EN would be set at both RC and EP by
pcie_config_aspm_link when the L1SS is supported
by the link.Signed-off-by: Richard Zhu
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Make sure that the sysfile api of the pcie ep is add properly.
Signed-off-by: Richard Zhu
Acked-by: Fugang Duan -
In the EP RC validation system, EP wouldn't set RC's
CLK_REQ# to low, like one real inserted EP device to do.
Let RC to set the over ride low and enabled, make sure that
REF_CLK of RC side is turned on.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
- Do not de-assert the clkreq# when compliance tests mode
is enabled, make sure that the ref_clk is turned on.
- Correct the PLL lock bit check point.
- Adjust the TRSV PHY registers to pass the compliance tests.Signed-off-by: Richard Zhu
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The generic PCI host controller is often instantiated by hypervisors, and
they may add several of them or add them in addition to a physical host
controller like the Jailhouse hypervisor is doing. Therefore, allow for
multiple domains so that we can handle them all.Signed-off-by: Jan Kiszka
Signed-off-by: Bjorn Helgaas
(cherry picked from commit 37bd62d224c8244bccdb1a5bd7833a48c9ba8a66)
(cherry picked from commit 9c363f4a6e5a420218b42f442d6beef0f2eb28f2)
Signed-off-by: Peng Fan -
Add support for unbinding the generic PCI host controller. This is
particularly useful when working in virtual environments where the
controller may come and go, but possibly not only there.Signed-off-by: Jan Kiszka
Signed-off-by: Bjorn Helgaas
CC: Will Deacon
CC: Lorenzo Pieralisi
(cherry picked from commit 01fcb7f777a9f5d216a1ff41228f15656e50fb63)
(cherry picked from commit 6a8a0e11c827908864cdd45623aa17b5bc80d2e5)
Signed-off-by: Peng Fan -
The only user of pci_get_new_domain_nr() is of_pci_bus_find_domain_nr().
Since they are defined in the same file, pci_get_new_domain_nr() can be
made static, which also simplifies preprocessor conditionals.No functional change intended.
Signed-off-by: Jan Kiszka
Signed-off-by: Bjorn Helgaas
Acked-by: Lorenzo Pieralisi
(cherry picked from commit ae07b786888f1872ac2b63d74a17e206d441ec9f)
(cherry picked from commit 3c52948d8a977b147e7b36172b9531eb2b7cb59d)
Signed-off-by: Peng Fan -
Enable the L1.1 ASPM support on iMX8MM, and
verified the EVK board.Signed-off-by: Richard Zhu
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- Enable the L1.1 ASPM support on iMX8MQ, and verified
on the both PCIe ports of the EVK board.
- Fix the L1 exit latency larger than 64us issue
Otherwise, the L1/L1.1 ASPM would be disabled in the
initialization.
- Add the internal PLL of the PCIe REF_CLK support, and
verify the L1.1 ASPM on port0 of 8MQ EVK boardSigned-off-by: Richard Zhu
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- warning: ‘retries’ may be used uninitialized in this function
- WARNING: vmlinux.o(.data+0x5d2d8): Section mismatch in reference from the
variable imx_pcie_driver to the function .init.text:imx_pcie_probe()The variable imx_pcie_driver references the function __init imx_pcie_probe()
If the reference is valid then annotate the variable with
__init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_consoleSigned-off-by: Jason Liu
Signed-off-by: Richard Zhu -
Fix the crash when pcie request the reserved memory region
after the -EPROBE_DEFER in the probe.
The pointer of the resource parameter would be invalided
in the second probe. Use one structure varible to replace
it.
Put node after done with it, after call of_parse_phandle.Signed-off-by: Richard Zhu
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PCIe ep rc validation is one remote processors communications.
Remove the hard-coded ep rc ddr test region on imx8 platforms.
Get the reserved region for ep rc ddr test region.Signed-off-by: Richard Zhu
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The perst signal shouldn't be asserted during imx6q/dl
pcie suspend.
Otherwise, the link would be down during resume,
and system would be hang.
Fix it by one return in imx6q switch case.Signed-off-by: Richard Zhu
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enable imx8mm pcie support.
BTW, the power management is not supported yet.
Disable pcie module, if you test power management
on the imx8mm platforms.Signed-off-by: Richard Zhu
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- They should be bitwise logic, not the boolean logic.
- Correct the error return values.Signed-off-by: Richard Zhu
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The DWC MSI controller does not support different MSI-X target addresses
and does not allow to route individual IRQs to different CPUs. Aside
from those shortcomings it is able to support MSI-X just fine.Some devices like the Intel i210 network controller depend on MSI-X to
be available to enable all hardware features, so even a feature limited
implementation of MSI-X on the host side is useful.Signed-off-by: Lucas Stach
Signed-off-by: Richard Zhu -
Replace the specific name imx6_xxx by imx_xxx.
Since all imx6/7/8 PCIe use the same driver.Signed-off-by: Richard Zhu
During 4.14 rebase remade this manually
Signed-off-by: Leonard Crestez
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Enable the imx pcie ep dma in the pcie ep rc
validation system.Signed-off-by: Richard Zhu
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Failed to verify the MSI in the EP RC system.
Root cause: the MSI address is not fetched corretly.
The second port of iMX8MQ EVK board should be used
as EP port, not the first one.Signed-off-by: Richard Zhu
Reviewed-by: Frank Li -
Enable the PCIE EP RC for iMX8
RC access memory of EP:
- EP:
write the to the bar0 of ep.
- RC:
access the , and this address
would be mapped to the of ep.
Note:
ddr_region_address mem_base_addr bar0_addr
imx8mq 0xb820_0000 0x2000_0000 0x33c0_0010
imx8qxp 0xb820_0000 0x6000_0000 0x5f00_0010
imx8qm 0xb820_0000 0x7000_0000 0x5f01_0010MSI verification:
- EP:
write 0 to the , for example ./memtool -32 =0
- RC:
check the msi is triggered or not.
cat /proc/interrupts | grep msi
Note:
The msi_addr can be get by the following command after RC platform
is boot up.
For example
root@imx8_all:~# dmesg | grep msi_addr
[ 2.670247] pci_msi_addr = 0x7ff80000, cpu_base 0x80000000msi_addr
imx8mq 0x27f8_0000
imx8qxp 0x6ff8_0000
imx8qm 0x7ff8_0000iMX8QM:
BuildInfo:
- SCFW daabd5d3, IMX-MKIMAGE 0ad6069a, ATF 93dd1cc
- U-Boot 2017.03-imx_v2017.03+gc662e0a
iMX8QXP:
BuildInfo:
- SCFW daabd5d3, IMX-MKIMAGE 0ad6069a, ATF 93dd1cc
- U-Boot 2017.03-imx_v2017.03+gc662e0aSigned-off-by: Richard Zhu
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To support the bus freq power saving mode, add the
sysfile interface.
request bus high: echo 1 > /sys/devices/platform/xxxxxxxx.pcie/bus_freq
release bus high: echo 1 > /sys/devices/platform/xxxxxxxx.pcie/bus_freqSigned-off-by: Richard Zhu
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Return the error when the pll is not locked.
Signed-off-by: Richard Zhu
Reviewed-by: Frank Li -
Enable the pcie pm on imx8qm/qxp
Signed-off-by: Richard Zhu
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Enable the PCIE PM on mScale.
- Refine the codes.Signed-off-by: Richard Zhu
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Driver should do defer probing if .of_get_named_gpio() returns -EPROBE_DEFER.
And moving epdev_on regulator to be common for all platforms.(BuildInfo: SCFW 3e70523d, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Fugang Duan
Reviewed-by: Richard Zhu -
Add the epdev_on regulator to power up the WiFi module
on the iMX8QM board.
This regulator needs to be powered up before the pcie
link, in order for the WiFi module to work.Signed-off-by: Fugang Duan
Signed-off-by: Tiberiu Breana -
Description:
Initial VCO oscillation may fail under corner conditions such as
cold temperature. It causes PCIe PLL fail to lock in
initialization phase.Project Impact:
iMX7D PCIe PLL fails to lock and PCIe doesn.t work.workarounds:
To disable Duty-cycle Corrector(DCC) calibration after G_RST
signal is de-asserted by following the sequences:
1. De-assert the G_RST signal by clearing
SRC_PCIEPHY_RCR[PCIEPHY_G_RST].
2. de-assert DCC_FB_EN in Reg4 by writing data '0x29' to the register
address 0x306d0014.
3. assert RX_EQS, RX_EQ_SEL in Reg24 by writing data '0x48' to the
register address 0x306d0090.
4.assert ATT_MODE in Reg26 by writing data '0xbc' to the register
address 0x306d0098.
5.De-assert the CMN_RST signal by clearing register bit
SRC_PCIEPHY_RCR[PCIEPHY_BTN].Signed-off-by: Richard Zhu
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- correct the msi address
- only do shutdown reset for imx6q pcie, since only
imx6qdl pcie doesn't have the reset mechanism.
- don't limit the max link speed of imx pcie to gen2Signed-off-by: Richard Zhu
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In order to make sure that get the regulator correctly.
Check the return value of devm_regulator_get().
Return value directly if it is '-EPROBE_DEFER'Signed-off-by: Richard Zhu
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Root cause:
Poewr domain of the PCIEs are turned off, and
not turned on properly in previous ATF.The PDs of PCIE1/2 have the dependency.
Both of the PDs should be operated at same time.
This issue is gone after update the PDs operations
in ATF.
In order to make sure that the PDs are turned on,
Turn power domain for imx8mq pcie explicitly in
driver.Signed-off-by: Richard Zhu
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On iMX8QM, functions of PCIEB relied on PCIEA.
But PCIEB used on iMX8QXP can work standalone.
Specify the iMX8QXP PCIE in driver.
Up to now, only iMX6QP PCIE may use the EXT OSC,
specify the EXT/EXT_SRC clocks for iMX6QP only.Signed-off-by: Richard Zhu
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The calibration value of PCIEA is mandatory required
by PCIEB on iMX8QM.The RSTs of the PCIEA would be cleared when the PDs
of PCIEA are turned off.
The calibration value of PCIEA would be lost when the
RSTs of PCIEA are cleared.
So, the RSTs of PCIEA should be asserted when enable
the PCIEB port. Otherwise, PCIEB wouldn't be functional.Signed-off-by: Richard Zhu
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- Both APB_RST_0 and APB_RST_1 should be asserted, when PHYX2
is used.
Otherwise, PHYX2 can't finish calibration.
- Correct the PCIEB(PHYX2_1) TX PLL locked check.
- The clear check of the reset should be done after
clks are enabledSigned-off-by: Richard Zhu
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The DBI_RO_WR_EN of PCIEB should be asserted,
otherwise the CLASS_DEVICE can't be configured
correctly, then PCIEB RC doesn't work at all.Signed-off-by: Richard Zhu
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The pcie_bus_regulator is only used by the iMX6QP board,
so only request the regulator for this variant.Signed-off-by: Tiberiu Breana
