23 Feb, 2019
2 commits
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Add delay cell support for fspi to set calibrated value to DLL register
for different clock frequency.Signed-off-by: Han Xu
(cherry picked from commit 5b608b98697668bd11563febba89bd0eea1c1b26) -
Several code changes to improve the i.MX8MM fspi performance.
- Implemented the SFDP lut to get the correct chip information
- Changed the default read mode from normal read to Quad DDR
- Enabled the AHB prefetch after chip probed
- Limited the highest clock rate for iMX8MMSigned-off-by: Han Xu
(cherry picked from commit c8dfe6ab108909a2e5bbc0ec11f3a24ad5b5844d)
12 Feb, 2019
38 commits
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Use ioremap_wc to handle unaligned qspi AHB read. Remove the previous
SW alignment handle for neat code.Signed-off-by: Han Xu
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Use ioremap_wc to handle unaligned flexspi AHB read. Remove the previous
SW alignment handle for neat code.Signed-off-by: Han Xu
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iMX8MM DDR3L validation board uses GD25LQ16 as spi-nor chip, but its
id is incorrect in ids table, so add a new id and parameters with the
same name into the ids table. For the same name of the chip info, the
log following we can ignore.LOG: m25p80 spi0.0: found gd25q16, expected gd25q16
Signed-off-by: Clark Wang
Reviewed-by: Fugang Duan -
Flexspi registers cannot be reset to default value, reset all FLASHxCR2
registers to 0 to avoid read data with invalid LUT commands.Signed-off-by: Han Xu
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The dummy pad settings should be align with data access mode, such as
set to PAD4 for all Quad read.Signed-off-by: Han Xu
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i.MX6QP and i.MX6ULL clock defination was missed in devdata.
Signed-off-by: Han Xu
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for 6UL/7D, the TDH bit should only be set when DDR mode enabled. This
bit cannot be cleared during module reset, so check this bit in
nor_setup to make sure it cleard and won't affect the following
operations.Signed-off-by: Han Xu
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runtime pm suspend should be called in error path during fsl-quadspi
driver probe. change the code to handle it properly.Add one more hwcaps SNOR_HWCAPS_READ_1_1_4 for the Spansion QSPI nor
s25fl128s since it only indicate this mode as the best performance mode
in SFDP table.Signed-off-by: Han Xu
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move the runtime pm get/put functions from nor_setup/nor_setup_last to
probe function to avoid runtime pm re-entrance issue.Signed-off-by: Han Xu
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decrese the AHB buffer size for AHB read as a workaround for random
UBIFS data corruptionSigned-off-by: Han Xu
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enable runtime suspend/resume for quadspi controller
Signed-off-by: Han Xu
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enable the ddr smp function to get correcct ddr sample point drom DT
Signed-off-by: Han Xu
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release the HIGH_FREQ request was done in runtime suspend, disable
autosuspend and disable the runtime in NAND probe error pathSigned-off-by: Han Xu
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Enabled the FlexSPI Octal DDR read for QXP, since all parameters for
this mode cannot be read from SFDP table, set the related parameters in
spi_nor_init_params.Signed-off-by: Han Xu
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re-init the flexspi controller after suspend/resume.
runtime resume will re-init the controller, Once the it was initialized
and need to be re-init(determined by read specific register bit).Signed-off-by: Han Xu
(cherry picked from commit fbc92b8524fde7cc048d4ccf603266e1b5e8734c) -
i.MX8MM MEK only supports Quad mode for flexspi nor, enable the quad ddr
mode for better performance.Signed-off-by: Han Xu
(cherry picked from commit a0abea8ca8d493fc2861c84f1475c0eb388899ce) -
Enable FlexSPI driver on i.MX8MM EVK.
Signed-off-by: Han Xu
(cherry picked from commit 0bb6d003fd6ce479308538a41f8a398beb70d897) -
enabled runtime pm for flexspi, also removed the redundant clock.
Tested with the latest SCFW and ATF.BuildInfo:
- SCFW 15d20cde, IMX-MKIMAGE ff9860c5, ATF
- U-Boot 2017.03-00003-gd09f5dbSigned-off-by: Han Xu
(cherry picked from commit 138fd5bb66dde0c1d391d5cff3ed5ef40ed3a212) -
FLEXSPI AHBCR register has one bit READADDROPT, which defined if start
address must be aligned when doing wordaddress access. This bit must be
set (no alignment limitation), otherwise controller may always try
to access from even address and got wrong data when AHB read data under
Octal DDR mode. Mounting UBIFS failed in this case since it read from
odd address.[ 250.367893] fsl_fspi_read: from 620ad1, len: 11
[ 250.374700] UBIFS error (ubi0:0 pid 2871): check_lpt_type: invalid
type (4) in LPT node type 2
[ 250.383326] CPU: 0 PID: 2871 Comm: mount Not tainted
4.9.11-03067-gd6ce90a-dirty #251
[ 250.391156] Hardware name: Freescale i.MX8QM ARM2 (DT)
[ 250.396291] Call trace:
[ 250.398739] [] dump_backtrace+0x0/0x1e0
[ 250.404139] [] show_stack+0x14/0x1c
[ 250.409198] [] dump_stack+0x8c/0xac
[ 250.414251] [] check_lpt_type+0x80/0x88
[ 250.419654] [] ubifs_lpt_init+0x448/0x8a4
[ 250.425222] [] ubifs_mount+0xde0/0x198c
[ 250.430620] [] mount_fs+0x3c/0x15c
[ 250.435589] [] vfs_kern_mount+0x4c/0x11c
[ 250.441077] [] do_mount+0x1b8/0xb5c
[ 250.446125] [] SyS_mount+0x78/0xd8
[ 250.451085] [] __sys_trace_return+0x0/0x4
[ 250.456787] ---lpt_init_rd
[ 250.459530] UBIFS (ubi0:0): background thread "ubifs_bgt0_0" stopsSigned-off-by: Han Xu
(cherry picked from commit deb1c43df234484e02f6eac758e78d2488bdd841)
- -
ARM64 platforms may access FSPI from non-64-bit-aligned address which
causes unalignment fault. Fixed the issue for AHB reading.Signed-off-by: Han Xu
(cherry picked from commit 948c1411230d5e02235fbd429d6ee2e2a2b9adb6) -
read_mode won't be used from 4.14 framework, switch it to hwcaps
Signed-off-by: Han Xu
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Some MICRON related macros in spi-nor domain were ST, actually. We
need to add the REAL micron defination in header/source files for
mt35xu512aba Micron Octal Nor chip.Signed-off-by: Han Xu
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Enhanced spi-nor framework to support octal read mode
Signed-off-by: Han Xu
Acked-by: Frank Li
(cherry picked from commit 95d0d54019ec291bf5430090dccb6dd66ea87de7) -
support the flexspi nor controller for i.MX8 platforms, read data
in octal ddr mode by default.Signed-off-by: Han Xu
Acked-by: Frank Li
(cherry picked from commit fba18ad064211c8612563edb4cd7ef63706cedba) -
To fix the i.MX6SX probe second chip error issue, add a dedicate AHB
read lut entry, The patch also remove the read length parameter for lut
preparation, which can be ignored.For the MICRON DDR read, constrain the dummy to up to 8 clock cycles.
Signed-off-by: Han Xu
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Enable the DDR mode with for SFDP. The code mapped the STR cmd to DTR
cmd and en/disable DDR module according to protocol type.Signed-off-by: Han Xu
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The patch based on yogesh dynamic lut patch(no spi-mem support) with minor changes.
Signed-off-by: Han Xu
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acquire/release dma in runtime pm resume/suspend to proper get/put dma
resources.BuildInfo:
- SCFW 60e110f9, IMX-MKIMAGE e131af10, ATF
- U-Boot 2017.03-imx_4.9.51_8qm_beta1_8qxp_alpha+gfcc9bdcSigned-off-by: Han Xu
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Remove the unnecessary tmp array from code
Signed-off-by: Han Xu
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Enable the EDO mode on i.MX8 platforms for better performance.
Signed-off-by: Han Xu
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for the large oob layout setting, need to calculate the correct free oob
space.Signed-off-by: Han Xu
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ARM64 platforms may access QSPI from non-64-bit-aligned address which
causes unalignment fault. Fixed the issue for AHB reading.Signed-off-by: Han Xu
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Enable the NAND support on i.MX8QXP
Signed-off-by: Han Xu
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mtd->priv is no longer pointing to the struct nand_chip it is attached
to. Replace those accesses by mtd_to_nand() calls.Signed-off-by: Octavian Purdila
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ULP1 use new QSPI NOR chip MX25R6435F which is not in default id table.
Signed-off-by: Han Xu
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QSPI only support upto 16 LUT slots while the QSPI commands are more
than this number, reserve the last two slots for dynamic change (most
commands used in pairs). Later all extra supported commands will be add
in dynamic lut table.Signed-off-by: Han Xu
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support QSPI on i.MX6ULL. By default, only QSPI1 was enabled, while
reworked board could support all 4 QSPI chips.Since i.MX6UL and i.MX6ULL QSPI controller are identical, reuse the
i.MX6UL datatype for i.MX6ULL.Signed-off-by: Han Xu
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support NAND on imx6ull
Signed-off-by: Han Xu
