24 May, 2016
6 commits
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Add pinctrls for usbotg1 and usbotg2 vbus control. This missing keeps
the vbus enable pin is high after power up, so vbus is on and otg port
will not enter suspend in device mode, as active usb port has high
bus freq requested, this prevents system enter low bus freq.Signed-off-by: Li Jun
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Add 'ipg' and 'axi' clocks for pxp which should
be used to control runtime power managments.Signed-off-by: Fancy Fang
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The pxp require two clocks to enable when it works, and
they are 'ipg' and 'axi' clocks. Besides, the two clocks
share the same CCGR to control clock gating.Signed-off-by: Fancy Fang
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The 'otm8018b' is the Source Driver IC which is used
by 'TFT3P5079E' panel. This patch is adding the build
support for the 'otm8018b' kernel driver.Signed-off-by: Fancy Fang
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Create a new dts for the 'TFT3P5079E' mipi panel on
imx7d sabresd revb board.Signed-off-by: Fancy Fang
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To avoid touch other bits of HW_ANADIG_SNVS_MISC_CTRL , use set/clear register
, and correct the bit29 setting:
--before: write 1 to toggle DDR power pin to high before enter DDR retention,
and write 1 again to pull pin to low when exit from DDR retention.
--now: write 1 to pull DDR power pin to high and write 0 to low.Signed-off-by: Robin Gong
16 May, 2016
1 commit
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This dts is only for USB HSIC controller test which needs
Validation Port Card on it.Disable controller 3 due to strange signal on it at arm2 board.
Signed-off-by: Peter Chen
(cherry picked from commit 8bd0739d81719ed8a09ca4e45393bb1c5ce3de83)
11 May, 2016
3 commits
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Add csis-clk-settle property to imx7D SDB mipi csi.
Signed-off-by: Sandor Yu
(cherry picked from commit 01365628fdfadc4f8343722a2d5c69d5d8037540) -
ov5647 mipi camera sensor is replaced by ov5640
on imx7D SDB RevB board.Signed-off-by: Sandor Yu
(cherry picked from commit aef2ab14e91ccd173086a9849cf64619e078ed6f) -
GPIO0~GPIO7 part:
- Commit(c8cabda5ab07) add some wrong input sel value for uart, return
them to origin setting.
- Add uart DTE pin mode setting.UART2_TX_DATA pin part:
- RM doc "iMX7D_RM_Rev0_Approval.pdf" (2016.04.25 updated in compass)
updated input sel define for UART2_RX_DATA, then set the correct input
sel for the pin.Signed-off-by: Fugang Duan
(cherry picked from commit: 90a8b06b9735dd5b8d2023ff3b95886441e0e8d9)
09 May, 2016
2 commits
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On i.MX7D, per design team's require, need to make sure
DLL is locked after DDR frequency scaled done. Although
normally there should be no issue, but it is better to
add it.Signed-off-by: Anson Huang
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On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.Signed-off-by: Anson Huang
08 May, 2016
2 commits
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i.MX7D TO1.2 removes the DDR PAD retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.Signed-off-by: Anson Huang
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i.MX7D 19x19 LPDDR2 ARM2 board's uSDHC1 CD pin should be
LOW active, correct it.Signed-off-by: Anson Huang
06 May, 2016
2 commits
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When A7 platform is in low power mode while M4 is NOT,
M4 should be able to send message to wake up A7, so
MU must be always as wake up source.Signed-off-by: Anson Huang
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Change when A7 signal M4 to make sure busfreq is
always up when the M4 send high bus release.
This prevents race condition for Low Power DemoSigned-off-by: Teo Hall
29 Apr, 2016
3 commits
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i.MX7d MAC1_ADDR fuse offset address is 0x640, i.MX6q/dl/sx/ul
MAC1_ADDR fuse offset address is 0x620. Correct it for i.MX7d,
otherwise read un-correct MAC address.Signed-off-by: Fugang Duan
(cherry picked from commit:74ee5313534dd9453601f4428c4916d46405669f) -
Set bcmdhd as build in type.
Signed-off-by: Haibo Chen
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i.MX7D TO1.2 fix the CKE issue, need to follow TO1.0's
precedure for DRAM frequency scaling.Signed-off-by: Anson Huang
20 Apr, 2016
1 commit
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For imx6sx-sabreauto board, the usdhc4 is used for the sd slot locate on the
base board, so need to improve the pad drive strength, otherwise we will meet
many CRC error or timeout error when insert a sd card.Signed-off-by: Haibo Chen
(cherry picked from commit 1cbfce01e4e076d7f7e3b879c2c41d217d8afa48)
19 Apr, 2016
2 commits
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SRTC needs to be kept enabled during system poweroff,
SNVS_LP control register bit 0 SRTC_ENV must be set
to enable RTC, for software poweroff, kernel just
read the register offset and value from dtb and write
to SNVS_LP control register to poweroff system, need
to make sure bit 0 SRTC_ENV is set to enable RTC during
system poweroff.Previous setting did NOT enable it which will cause
RTC stop running if using software poweroff.Signed-off-by: Anson Huang
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Need to make sure build pass with single SOC
config, in current build for single SOC config,
if both SOC_IMX7D and SOC_IMX6SX are NOT selected,
below build error will occur, add MU module
config to fix this build issue.LD init/built-in.o
arch/arm/mach-imx/built-in.o: In function `busfreq_probe':
:(.text+0x5370): undefined reference to `imx_mu_lpm_ready'
arch/arm/mach-imx/built-in.o: In function `bus_freq_pm_notify':
:(.text+0x5d50): undefined reference to `imx_mu_lpm_ready'
:(.text+0x5d68): undefined reference to `imx_mu_lpm_ready'
make: *** [vmlinux] Error 1Signed-off-by: Anson Huang
12 Apr, 2016
2 commits
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In the OCOTP fuse map, the speed grading[1:0] define the MAX
CPU speed the chip can run. The detailed definition is below:
2b'00: Reserved;
2b'01: 528000000Hz;
2b'10: 696000000Hz;
2b'11: Reserved;We need to disable the illegal setpoints according to the fuse map.
Signed-off-by: Bai Ping
(cherry picked from commit 1fc5419ba08a8da302cfcddb0ea76226d7bdc8c3) -
According to the latest datasheet(Rev. 0, 12/2015),
When the chip is run at LDO enabled mode, the highest
setpoint can be set to 700MHz in overdrive mode.Signed-off-by: Bai Ping
(cherry picked from commit 9838ff4b9dfaaacdea01b2bf5f54020ccf991f23)
31 Mar, 2016
1 commit
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Q901 (IRLML6401) is p-channel MOSET, need set pin1 (LCD_nPWREN) to low
to let pin3 output be 3V3. Normally when pin1 is high, then pin3
output should be gated. It was working previously due to some leakage.
Correct the enable logic from the software viewpoint.Signed-off-by: Robby Cai
(cherry picked from commit c70398a0b2e860d0bd9478d956d077eff8e7ea4f)
21 Mar, 2016
1 commit
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Below are the differences between standard evk:
- Enable tpl
- Enable software control vbus for otg2 (hardware rework is needed)
- Disable TSC due to the pin conflict with above vbus regulatorSigned-off-by: Peter Chen
(cherry picked from commit e4a5f2e763d5c9df8b97b01ee38879a9bee66f0d)
15 Mar, 2016
1 commit
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CMA region is a must to avoid the multile memory mapping
for the DMAed memory and also benifit the large continious
phisical memory allocation.The default value is depend on the target system design and
user cases definition. This is not suitable to put this into
the soc.dtsi, thus we put it into the board DTS.customer can override the value by changing cma size in DTS file.
Again, customer need set the CMA size correctly according to the
target system. The incorrectly CMA size can cause Linux kernel fail
to boot up.CMA disabled or CMA size set to zero is also not allowed.Signed-off-by: Jason Liu
04 Mar, 2016
1 commit
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add lpsr mode state for flexcan pins
Signed-off-by: Dong Aisheng
(cherry picked from commit 535699f47fbd7fb22a435ca2047560ee20687392)
02 Mar, 2016
1 commit
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There have two same extended enet dts file to enable fec2 port, so
remove the redundant enet dts file.The issue is caused by the commit 370426c2a918 that was cherry picked
after commit b74c6b9c7fdc.Signed-off-by: Fugang Duan
01 Mar, 2016
2 commits
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MMC core pm_notify will re-detect card after system suspend/resume,
regardless of post-cd claim.
Since in current MMC implement, non-removeable card only detects once,
this will break post card detect which happens next.
e.g. when we suspend/resume system first, then load Broadcom wifi module,
we will get below dump:root@imx6qdlsolo:/mnt/nfs/vte_IMX6QP-Sabre-SD# modprobe bcmdhd firmware_path=/lib/firmware/bcm/ZP_BCM4339/fw_bcmdhd.bin nvram_path=/lib/firmware/bcm/ZP_BCM4339/bcmdhd.ZP.SDIO.cal
dhd_module_init in
Power-up adapter 'DHD generic adapter'
wifi_platform_bus_enumerate device present 1
failed to power up DHD generic adapter, 3 retry left
wifi_platform_bus_enumerate device present 0
-----------[ cut here ]-----------
Kernel BUG at 80513170 [verbose debug info unavailable]
Internal error: Oops - BUG: 0 1 PREEMPT SMP ARM
Modules linked in: bcmdhd ov5642_camera ov5640_camera_mipi_int ov5640_camera_int mxc_v4l2_capture mxc_dcic ipu_bg_overlay_sdc ipu_still v4l2_int_device ipu_prp_enc ipu_csi_enc ipu_fg_overlay_sdc
CPU: 1 PID: 1487 Comm: modprobe Not tainted 4.1.15-1.0.0+g54cf6a2 #1
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
task: a881e3c0 ti: a9152000 task.ti: a9152000
PC is at mmc_sdio_remove+0x7c/0x80
LR is at mmc_sdio_force_remove+0xc/0x34
pc : [] lr : [] psr: 60030013
sp : a9153d28 ip : 00000000 fp : 00000000
r10: 00000000 r9 : 00000000 r8 : 7f0f76e0
r7 : a9153d58 r6 : 00000000 r5 : 00000000 r4 : a83f1800
r3 : 00000000 r2 : 00000000 r1 : 809c02f4 r0 : a83f1800
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 38d7804a DAC: 00000015
Process modprobe (pid: 1487, stack limit = 0xa9152210)
Stack: (0xa9153d28 to 0xa9154000)
3d20: 00000000 7f0c569c a9ffe440 00000003 00000000 7f0c58f4
3d40: a81942c0 8032e33c a8195960 7f0fbf68 00020002 00000000 a9153d58 a9153d58
3d60: fffffdfb 80bc0db4 a81af810 7f0f9518 fffffdfb 00000008 00000000 5624ce5c
3d80: 00000124 80381140 80bc0db4 a81af810 7f0f9518 00000000 00000008 8037f9dc
3da0: a81af810 7f0f9518 a81af844 80b288b0 00000000 8037fbec 00000000 7f0f9518
3dc0: 8037fb60 8037e068 a8025c5c a818fa34 7f0f9518 a20ff280 00000000 8037f16c
3de0: 7f0f0330 a9ffe440 00000000 7f0f9518 a9ffe440 00000000 80bb18f4 803801ec
3e00: 7f0fbf68 a9ffe440 00000000 7f0c5fdc 80b01720 80b01720 a9ffe440 7f11f000
3e20: 00000000 00000001 5624ce5c 80009730 abc7b120 800e316c 000000c8 a9209a00
3e40: 8040003f 00000001 00010000 800b0dfc 000000c8 8040003f abc7dc60 80afc2b0
3e60: abc75880 80afc260 a8001f00 80afe6c0 00000124 800e4944 7f0f9718 00000001
3e80: 7f0f9718 00000001 a9ffeb00 7f0f9718 a9db31c0 8078e47c 7f0f9718 a9db31c0
3ea0: a9153f58 00000001 a9db31c8 80094094 7f0f9724 00007fff 800910d4 00000000
3ec0: 00000000 7f0f9760 00000000 7f0f9860 c0fce8f4 7f0f9724 00000000 8079aa0c
3ee0: c0f07000 000c7944 00b6817a 00000000 0000000e 00000000 00000000 00000000
3f00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3f20: 00000000 00000000 00000000 00000000 00000640 00000000 00000003 01608348
3f40: 0000017b 8000f604 a9152000 00000000 01608270 800944f8 c0f07000 000c7944
3f60: c0fce28c c0f83439 c0f99248 0007aff8 0008f968 00000000 00000000 00000000
3f80: 00000029 0000002a 00000020 00000024 00000015 00000000 01608348 00000073
3fa0: 00000000 8000f480 01608348 00000073 00000003 01608348 00000000 00000000
3fc0: 01608348 00000073 00000000 0000017b 01608218 00000000 00000073 01608270
3fe0: 7e9ab8c0 7e9ab8b0 0001f2c0 76eac340 600d0010 00000003 00000000 00000000
[] (mmc_sdio_remove) from [] (dhd_wifi_platform_load+0x180/0x39c [bcmdhd])
[] (dhd_wifi_platform_load [bcmdhd]) from [] (platform_drv_probe+0x44/0xac)
[] (platform_drv_probe) from [] (driver_probe_device+0x174/0x2b4)
[] (driver_probe_device) from [] (__driver_attach+0x8c/0x90)
[] (__driver_attach) from [] (bus_for_each_dev+0x68/0x9c)
[] (bus_for_each_dev) from [] (bus_add_driver+0x148/0x1f0)
[] (bus_add_driver) from [] (driver_register+0x78/0xf8)
[] (driver_register) from [] (dhd_wifi_platform_register_drv+0x1bc/0x208 [bcmdhd])
[] (dhd_wifi_platform_register_drv [bcmdhd]) from [] (do_one_initcall+0x8c/0x1d4)
[] (do_one_initcall) from [] (do_init_module+0x5c/0x1a8)
[] (do_init_module) from [] (load_module+0x1ba8/0x1e50)
[] (load_module) from [] (SyS_finit_module+0x80/0x90)
[] (SyS_finit_module) from [] (ret_fast_syscall+0x0/0x3c)Signed-off-by: Dong Aisheng
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The pwm1's pin belongs to lpsr iomux. So this should
be corrected.Signed-off-by: Fancy Fang
(cherry picked from commit 94f87fc66f354dea8537d360732612ac5d6d65e6)
29 Feb, 2016
1 commit
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Add ADC support for imx7d-12x12-lpddr3-arm2 board.
Signed-off-by: Haibo Chen
26 Feb, 2016
1 commit
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Add spi1 IOMUX sleep state in imx7d-12x12-lpddr3-arm2.dts.
Signed-off-by: Gao Pan
25 Feb, 2016
1 commit
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Add 100Mhz (HIGH_AUDIO_CLK) bus frequency support for imx6q lpddr2 targets
On HIGH_AUDIO_CLK busfreq request source dram mmdc clock root from
pll2_pfd2_div_2 to generate 100Mhz operation frequency.Signed-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry-picked from commit 5bc118112b36b72ed6b1e75a3760c371b486abec)
24 Feb, 2016
1 commit
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Before entering LPSR mode, as GPC was set to STOP/DSM mode already,
the wfi loop after LPSR mode would cause system enter STOP/DSM mode
first, then SNVS will force PMIC_ON_REQ to low, as SNVS needs IPG
clock to be on before entering SNVS/LPSR mode, so we have to disable
STOP/DSM mode to make sure IPG clock is on before SNVS actually enters
LPSR mode.Signed-off-by: Anson Huang
23 Feb, 2016
1 commit
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In the lpddr3-arm2-m4 dts, the I2C1 is disabled, so PMIC is disabled,
the cpufreq is not support. As thermal driver is depended on cpufreq
driver, if cpufreq is not support, the tempmon device can be disabled.Signed-off-by: Bai Ping
22 Feb, 2016
2 commits
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Wait PU LDO ramp before GPU power on once system resume back on i.mx6qp,
otherwise, GPU resume may hang.Signed-off-by: Robin Gong
(cherry picked from commit 361af86190c160e0ea66e007c61b18a793149b74)
(cherry picked from commit 7ddd834bde557db1b62ea2ae683455cc75ba858e) -
The 'csi_sel' clock is in ccm instead of anatop.
So correct the wrong register address used.Signed-off-by: Fancy Fang
(cherry picked from commit 2a1a58c63f4aeba3733f74efdaef3784186ef15c)
21 Feb, 2016
1 commit
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Before changing the ARM_PODF, the pll1_bypass clock should be enabled and
bypassed to make sure the ARM_PODF can be changed.Signed-off-by: Bai Ping
(cherry picked from commit 78916c528cb424b20e87887c85246fceac81f3b4)
19 Feb, 2016
1 commit
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PU can be dynamically turned off or on, so we need remove
"regulator-always-on" property.Signed-off-by: Robin Gong
(cherry picked from commit f3c0df15fbecce36cae531a4a919d544f9ea8e2a)