29 Aug, 2017
1 commit
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Add focaltech new touch panel ft5246 support.
Set the ft5426 as default panel for dts. If want to use the old panel, then
it needs to boot with imx7ulp-evk-ft5416.dtb file.Signed-off-by: Fugang Duan
12 Jul, 2017
1 commit
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Add pxp v3 crop feature support.
Update the pxp_dma.h file.Signed-off-by: Guoniu.Zhou
(cherry picked from commit 23da5fe99a89adde6a8943517e0d7042dad50ea3)
15 Jun, 2017
1 commit
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According to commit b073ed4e2126 ("ASoC: soc-pcm: DPCM cares BE format"),
Current DPCM only care FE channel, but it will set unsupported channel to
drivers.
So add dpcm_merged_chan, which is used to merge the BE's codec
channels configuration to FE if it exist in snd_soc_dai_link. And
dpcm_runtime_base_chan function is to get the channel configuration of BE,
which likes the dpcm_runtime_base_format function.Signed-off-by: Shengjiu Wang
09 Jun, 2017
17 commits
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Remove whitespace.
Signed-off-by: Irina Tirdea
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When 'CONFIG_MXC_PXP_CLIENT_DEVICE' disabled, the
'register_pxp_device' and 'unregister_pxp_device'
may cause multiple definitions compiling error.Signed-off-by: Fancy Fang
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The latest pxp_dma.h file change PXP_PIX_FMT_RGB32 to PXP_PIX_FMT_XRGB32 format,
but the userspace still use PXP_PIX_FMT_RGB32, so add back it and keep the same
with PXP_PIX_FMT_XRGB32 format.Signed-off-by: Guoniu.Zhou
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The V3 version PXP has added below new 2D features:
1. Input fetch/store blocks to accept different formats input/output.
2. Add Rotation1 block to do rotation before alpha blending.
3. Add Composite1 block to accept source from input fetch.
4. AS and PS have increased supported pixel formats.Signed-off-by: Fancy Fang
Signed-off-by: Guoniu.Zhou
(cherry picked from commit 4daef24b19890ca65135c48fc24018f64761444f) -
Add several new pixel formats definition which are supported
by PXP V3 ip.Signed-off-by: Fancy Fang
(cherry picked from commit 5195602ac0225902bd416647fb9cd0636fa11e89) -
Some RGB formats fourcc definition are not precise
according to its original meaning. So make some
changes for them.Signed-off-by: Fancy Fang
(cherry picked from commit b0b4ad680e267bdf542d2c9a3202c0192bde9cb0) -
According to the pxp high level architecture diagram,
it is better to divide the whole big pxp module into
four sub-modules:
1. 2D operation module(legacy pxp and input fetch & store).
2. Dithering module.
3. WFE_A module.
4. WFE_B module.
This division will simplify driver implementations and
management.Signed-off-by: Fancy Fang
(cherry picked from commit 5e57840b41adb195515bd652d9624feaadf3448e) -
Add 'need_yuv_swap' field to 'pxp_proc_data' structure to
record the yuv formats which needs byte swap.Signed-off-by: Fancy Fang
(cherry picked from commit 28ce43b27faad915e93f47b438d23f4ebfe020b5) -
The multiple overlay layers are not used on pxp v2 and
v3 module, so remove this.Signed-off-by: Fancy Fang
(cherry picked from commit c4fd8b36dbf9b53079d88d55ccfedde3a444ec29) -
There are no busfreq methods implemented for
ARM64, so use the dummy methods in this case.Signed-off-by: Viorel Suman
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Add off_on_delay for fixed regulator. This can assign the delay time
between the regulator disable and regulator enable.User can define the delay value by using 'off-on-delay' in dts file.
Signed-off-by: Haibo Chen
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Add rpmsg-keys driver on i.mx7ulp-evk board since vol+/vol- keys
are connected on m4 side and have to get the status of keys by
rpmsg.Signed-off-by: Robin Gong
[Irina: updated for 4.9 APIs]
Signed-off-by: Irina Tirdea -
USB phy driver may need to know the current working mode of
the controller, and does some different settings according to
host mode or device mode.Signed-off-by: Li Jun
(cherry picked from commit 2286cb30feedd6f4a5cb82a0f0af5aa3a04ab698) -
Implement the initial driver for the I2C device
ADV7535.Signed-off-by: Fancy Fang
(cherry picked from commit 274e17dd0cb6068a94103c948aa1a032e52b8efa) -
MMC SDHCI maintainer Adrian Hunter Introduce SDHCI flags for signal
voltage support and set them based on the supported transfer modes,
except in the case where 3V DDR52 is supported but 1.8V is not.This patch add the support to make eMMC DDR52 only work at 3.3v when
property 'no-1-8-v' defined.Signed-off-by: Haibo Chen
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In some platforms, accessing registers needs to make sure
power domain is enabled, such as for clock operations, power
domain needs to be enabled first before accessing clock
registers, so some clocks need to know its power domain's
status, it will need to get power domain structure by phandle,
expose the API to support this case.Signed-off-by: Anson Huang
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add focaltech touch screen support
Signed-off-by: Gao Pan
(cherry-pick from 595cefbee5586e77ceb9ad900c256177a98367c7)
08 Jun, 2017
20 commits
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- let the arch/arm/mach-imx/mu.c do the
AMP PM only, add the IRQF_SHARED to its isr.
- remove the rpmsg implementations in this
mu driver.Signed-off-by: Richard Zhu
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- add the MU version1.0 (introduced by 7ulp)
support.
- add the MU_SetFn and MU_ReadStatus APIs.
- fix one mispell bug when enable the RX INTs.
Otherwise, the RX INTs wouldn't be configured
correctly.Signed-off-by: Richard Zhu
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Remove the TI wifi from defconfig and include the head file host.h
which contain the definition of struct mmc_host to avoid the following
compile warning:In file included from drivers/net/wireless/ti/wlcore/sdio.c:28:0:
./include/linux/mmc/sdio.h:193:35: warning: 'struct mmc_host' declared inside parameter list
void mmc_sdio_force_remove(struct mmc_host *host);
^
./include/linux/mmc/sdio.h:193:35: warning: its scope is only this definition or declaration, which is probably not what you wantSigned-off-by: Haibo Chen
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Add HSRUN mode clocks on i.MX7ULP. we also add a fake clock mux ARM
to make the clock tree more easy to handle in cpufreq.Signed-off-by: Bai Ping
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Add gpt_3m clock source on i.MX6SLL.
Signed-off-by: Bai Ping
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Fix following build error by changing type to '__u64'.
include/uapi/linux/pxp_dma.h:230:2: error: unknown type name 'u64'
u64 lut_sels;
^~~Signed-off-by: Robby Cai
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Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLKIMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.
Update copyright information.
Signed-off-by: Fugang Duan
Signed-off-by: Adrian Alonso -
- change from wfe_b to wfe_a, and modifiy register settings to support new flow
- the underlying design policy change as follows.
in previous flow, when all LUTs are used, the LUT cleanup operation
need to wait for all the LUT to finish, it will not happen util last LUT
is done. while in new flow, the cleanup operation does not need to wait
for all LUTs to finish, instead it can start when there's LUT's done.
The saved time is multiple LUT operation time.Signed-off-by: Robby Cai
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update driver since m4 side refine the header structure.
Signed-off-by: Robin Gong
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The MIPI DSI controller on imx7ulp board comes from NorthWest Logic
which is a completely new DSI module. And this is the driver code
for the new IP.Signed-off-by: Fancy Fang
(cherry picked from commit 99ea590f9898b876215baf70c2f0a7112fc15ad3) -
Need ensure the cma reserved region not cross the low/high memory boundary
when using the dynamic allocation methond through device-tree, otherwise,
kernel will fail to boot up when cma reserved region cross how/high mem.Signed-off-by: Jason Liu
Cc: Laura Abbott
Cc: Frank Rowand
Cc: Rob Herring
Cc: stable@vger.kernel.org -
On i.MX6SLL, if all PLLs is bypassed in low power run mode, we can decrease
the VDD_ARM_IN and VDD_SOC_IN voltage to 0.925V to save power. a 25mV margin
is added to cover IR drop and board tolerance.Add low power run voltage change support for i.MX6SLL.
Signed-off-by: Bai Ping
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At imx7ulp, if the system enters idle, it will close some clocks and affect
USB transfer. In order to avoid it, we request pmqos to avoid system
entering idle when the USB is in use.Signed-off-by: Peter Chen
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The two extcon notifiers are almost the same except for the
variable name for the cable structure and the id notifier inverts
the cable->state logic. Make it the same and replace two
functions with one to save some lines. This also makes it so that
the id cable state is true when the id pin is pulled low, so we
change the name of ->state to ->connected to properly reflect
that we're interested in the cable being connected.Cc: Peter Chen
Cc: Greg Kroah-Hartman
Cc: "Ivan T. Ivanov"
Signed-off-by: Stephen Boyd
Signed-off-by: Peter Chen -
We're currently emulating the vbus and id interrupts in the OTGSC
read API, but we also need to make sure that if we're handling
the events with extcon that we don't enable the interrupts for
those events in the hardware. Therefore, properly emulate this
register if we're using extcon, but don't enable the interrupts.
This allows me to get my cable connect/disconnect working
properly without getting spurious interrupts on my device that
uses an extcon for these two events.Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Cc: "Ivan T. Ivanov"
Fixes: 3ecb3e09b042 ("usb: chipidea: Use extcon framework for VBUS and ID detect")
Signed-off-by: Stephen Boyd
Signed-off-by: Peter Chen -
SAI in M4 domain, and the clock used by SAI is in M4 domain
Signed-off-by: Shengjiu Wang
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Add i.MX7ULP clock driver.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Fancy Fang -
Add the AFT_ENABLE event macros, because that
1.8v of imx7d pcie phy, should be turned on after
the 1p0d(1.0v) of pcie phy is turned on.Signed-off-by: Richard Zhu
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add extern audio clock in imx6sll clock tree
Signed-off-by: Shengjiu Wang
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correct VMINSYS_MASK and _CNFG_REGTEMP_MASK define for regmap
Signed-off-by: Robin Gong
