23 Feb, 2017
40 commits
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This driver is based on the current code which runs the the EMV test on the i.MX258 platform.
Since there are still many cases that can't pass on the i.MX258 and i.MX7d platform. The
driver will need to be improved after per-test work. Just check in as a base code. There
would be definitly some timing improvement work to do in the future.Signed-off-by: Luwei Zhou
(cherry picked from 3ac1ad5b2a68ecb052ccacca4ac7459ead04415e) -
Enable cpuidle for i.MX7D, total 3 level idle supported:
1. ARM WFI;
2. WAIT mode;
3. Low power idle with ARM/SCU platform power off.Only when system in low bus freq mode, system is able to
enter low power idle, and only when both of 2 cores are
in low power idle, ARM/SCU platform will be powered off.DDR will be put into low power mode when low power idle
is entered.Signed-off-by: Anson Huang
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To achieve low power, debug uart clk should be from OSC, so that
it does NOT need to keep PLL on, especially for low power idle
case.Signed-off-by: Anson Huang
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There is official workaound for TKT238285, so remove the limitation
for i.mx6dl.Signed-off-by: Robin Gong
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Enable ecspi dtb for imx7d-12x12-lpddr3-arm2 board.
Signed-off-by: Robin Gong
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We set both wartermark of txfifo and rxfifo 32 as half of fifo length 64.
That will cause easy rxfifo overflow:
If there is 31 bytes in rxfifo, rx script will wait the next dma request
(the 32th data come into the rxfifo) and schedule out to tx script. Once
tx script start to run, the rx script need to wait tx script finish even
if its priority higher than tx. Meanwhile, spi slave device may input
data continous, plus the rx data which triggered by new tx script(32 bytes).
That will quickly consume whole 64 bytes fifo, so we keep 16bytes availbale
even in the worst case new tx script triggered during two rx transfer. That
may slow down tx slightly, but better than overflow and RX DMA timeout.Signed-off-by: Robin Gong
(cherry picked from commit 16043ad0ad96aa04a90614e473aa17980af4b8af)
(cherry picked from commit 819efee83b7b1f47685dca6fad6bbe17f1c42092)
(cherry picked from commit 5c4c7d05bbba0ea2b26ef2f3ae83119d5eada235) -
There is occasion that dma callback come late after the substream is released.
Then there will be kernel dump.[] (imx_pcm_dma_complete) from [] (sdma_handle_channel_loop.isra.25+0x48/0x54)
[] (sdma_handle_channel_loop.isra.25) from [] (sdma_tasklet+0xa0/0x1d4)
[] (sdma_tasklet) from [] (tasklet_action+0x64/0xf8)
[] (tasklet_action) from [] (__do_softirq+0x104/0x218)
[] (__do_softirq) from [] (irq_exit+0xa8/0xec)
[] (irq_exit) from [] (handle_IRQ+0x3c/0x90)
[] (handle_IRQ) from [] (gic_handle_irq+0x28/0x5c)
[] (gic_handle_irq) from [] (__irq_svc+0x40/0x70)The reason is the sdma tasklet is async with audio substream release. ALSA
think when terminate dma, the dma should be stopped and no callback be called.This patch is to add new api dma_sync_wait_tasklet(), which is called in
snd_dmaengine_pcm_close(). It will make sure the callback not be called
after this funtion. Tasklet_kill is to wait scheduled tasklet end.Tasklet_kill can't be added to terminate dma function, because terminate dma
function may be called in interrupt, but tasklet_kill can't be called in
interrupt context.Signed-off-by: Shengjiu Wang
(cherry picked from commit 9815881b6acaa72a705e1fa3c26a852fc81bfce5) -
As SSI has dual fifo, add src_dualfifo and dst_dualfifo in imx_dma_data
to support dual fifo in DMA_DEV_TO_DEV.Signed-off-by: Shengjiu Wang
(cherry picked from commit cfde1308f170166a0099ca39ee8733895f9626f0) -
Use SET_LATE_SYSTEM_SLEEP_PM_OPS rather than the common sleep pm ops to ensure
sdma has resumed back before all other module drivers which use sdma resume
back.Signed-off-by: Robin Gong
(cherry picked from commit a7f8725509b494c3073b1bcca63252d5c61bb80d) -
Enable Mega/Fast support for i.mx7d. Need save and restore SDMA registers.
Signed-off-by: Robin Gong
(cherry picked from commit 4e1ea64c5d360ebc4f8168c1fcdee314b547bd13) -
The SDMA driver not consider the case of event_id0 is 0. That make uart6 rx
not working.Signed-off-by: Robin Gong
(cherry picked from commit dbcacbcb3a885d7569e9e415035b1dd06c4a117b)
(cherry picked from commit 6dfdbe41a7d6ab7e6fae5d6fb4d73435839beff3) -
Current ecspi rom script didn't take care of rxfifo overflow risk. Add new
ecspi tx script to check the rxfifo status, if it is near to full(>=48 bytes),
do not copy data to txfifo which will trigger data push into rxfifo. Because
rx script may not read rxfifo in time, we have to consider it.Signed-off-by: Robin Gong
(cherry picked from commit 17f472aa698aba0af5da4566df447e23306f4289)
(cherry picked from commit 90c929d7d1a3f8e196641b5ed7a33d2ee03bd63c)
(cherry picked from commit 6d76bdcf2097e4198217edf27363cf6ba2e6542a) -
cherry-pick below patch from v3.14.y:
ENGR00319473: dma: imx-sdma: support sdma restore from
mega/fast power down statusSupport sdma suspend and resume interface to restore from mega/fast power down.
Signed-off-by: Robin Gong
(cherry picked from commit 682fd1f47ab9cb69382fa0e8d20a830ae99c26fc)
(cherry picked from commit dd17fa18b9a0c11f8bce3b87f792775d96e461c1) -
This patch is just created by so many confilict while cherry-pick
from v3.10 a6a6cf911f85a3a09f763195478d422c571b9565.Signed-off-by: Robin Gong
(cherry picked from commit c070364148de0331152700850f5cb5577dbb504e) -
cherry-pick below patch from v3.14.y:
ENGR00329948-3: dma: imx-sdma: Add hdmi audio support
in sdmaThere's a missing script for hdmi audio support in current sdma driver,
thus add it.This HDMI script doesn't use bd to copy memory like a normal one does
but only to update the memory address for HDMI internal AHB DMA and
then trigger its procedure automatically.Signed-off-by: Shengjiu Wang
Signed-off-by: Robin Gong
(cherry picked from commit dafddac916a03ae4477e2de7c1b7ad291f956f68) -
ENGR00286273-1 dma: imx-sdma: allocate memory from iram
We try to allocate memory from SoC internal SRAM so that we can turn off
voltage of external DDR to save power. Surely, if we failed to get the
iram DT node or allocate memory due to no enough SRAM space, we would
allow SDMA driver to allocate memory in a traditional way.Signed-off-by: Nicolin Chen
Signed-off-by: Robin Gong
(cherry picked from commit f6924fbdb90d1f01266fc018caff953457e04d34)
(cherry picked from commit 7b643e5c9119ac43b937816fd1b785d2b859b05f) -
For UART, we need use old chn_real_count to know the real rx count even in
cylic dma mode, because UART driver use cyclic mode to increase performance
without any data loss.Signed-off-by: Robin Gong
(cherry picked from commit 398cee2ad110c4f183e553af0564fbdcbe8548cb) -
cherry-pick below patch from v3.14.y:
ENGR00329822-01 dmaengine: imx: fix loop mode issue
Fix loop mode issue that calling dmaengine_tx_status() can get
right state.residue value.Signed-off-by: Fugang Duan
Signed-off-by: Robin Gong
(cherry picked from commit 37e17f10b35c34317def08704e4b4edf5aa23894)
(cherry picked from commit 00cc7021317ac6efb460eb1b9bc3bd8aa6ad73c2) -
Add new ecspi and qspi script.
Signed-off-by: Robin Gong
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add sdma firmware for i.mx6 and i.mx7d
Signed-off-by: Robin Gong
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Correct "cpu0" node in alphabetical sequence.
Signed-off-by: Robin Gong
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the PFD override bit must be set before system entering any low power mode.
Signed-off-by: Bai Ping
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GPT1 clk root must be enabled, as GPT1 is system's clk
source.Signed-off-by: Anson Huang
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This patch updates all clk driver from L3.14.y, as
cherry-pick all clk related patch needs to handle
about 40 patches conflicts, so just copy it from
L3.14.y as it is an independent driver, for commit
log, please refer to L3.14.y.Signed-off-by: Anson Huang
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Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:&clks {
assigned-clocks = ,
;
assigned-clock-parents = ,
;
};The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf
Signed-off-by: Ranjani Vaidyanathan
Signed-off-by: Fabio Estevam
Signed-off-by: Philipp Zabel
Reviewed-by: Akshay Bhat
Tested-by Joshua Clayton
Tested-by: Charles Kang
Signed-off-by: Shawn Guo -
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. As this can not be guaranteed by
the clock framework during runtime, make the ldb_di[x]_sel muxes read-only.
A workaround to set the muxes once during boot could be added to the
kernel or bootloader.Signed-off-by: Philipp Zabel
Signed-off-by: Fabio Estevam
Signed-off-by: Shawn Guo -
MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the
parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never
succeed.
Disable the handshake mechanism to allow changing the frequency of
mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI
clock.Signed-off-by: Philipp Zabel
Signed-off-by: Fabio Estevam
Signed-off-by: Shawn Guo -
APBH DMA needs NAND clk to be enabled, its driver
does NOT handle this clk very well, so kernel
will boot up fail without NAND clk enabled, so
disable APBH DMA by default.Signed-off-by: Anson Huang
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This patch adds busfreq support for i.MX7D 12x12-lpddr3-arm2
board, the busfreq setpoint definition is same as imx7d-sdb
board.Signed-off-by: Anson Huang
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Porting the pxp-v4l2 output driver to imx_4.1.y branch.
Signed-off-by: Fancy Fang
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Add dts support for pxp-v4l2-output module for
imx7d-sdb board.Signed-off-by: Fancy Fang
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Add dts support for pxp-v4l2-output module for
imx7d-12x12-lpddr3 board.Signed-off-by: Fancy Fang
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cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().Signed-off-by: Haibo Chen
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Add request_bus_freq() and release_bus_freq() calls to the
various drivers to ensure that the DDR and AHB are the requested
frequency before the driver starts its task.Signed-off-by: Fugang Duan
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Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.Signed-off-by: Anson Huang
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This patch adds busfreq support for i.MX7D SDB
board with DDR3 memory, 3 setpoints supported:HIGH: DRAM CLK = 533MHz, AXI = 332MHz, AHB = 135MHz;
AUDIO: DRAM CLK = 100MHz; AXI = 24MHz, AHB = 24MHz;
LOW: DRAM CLK = 24MHz; AXI = 24MHz, AHB = 24MHz;Signed-off-by: Anson Huang
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* Fix PLL Audio/Video Numerator/Denominator register offsets
* In imx7d pll register CCM_ANALOG_PLL_VIDEO_NUM and
CCM_ANALOG_PLL_VIDEO_DENOM offset is different with imx6.
For imx7D the correct setting should be:
PLL_NUM_OFFSET 0x20
PLL_DENOM_OFFSET 0x30
* Add additional macros to handle imx7d audio/video
pll num/demom offset settings.Signed-off-by: Adrian Alonso
[Octavian: use IMX_PLLV3_AV_IMX7 instead of cpu_is_imx7d()]
Signed-off-by: Octavian Purdila -
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.There is a test_div placed before DRAM PLL's gate, so
add this test div clk.Signed-off-by: Anson Huang
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It's excessive to use prefix for the parameters when you do
modprobe mmc-block mmcblk.perdev_minors=16Make this available only for built-in case.
Signed-off-by: Andy Shevchenko
Signed-off-by: Ulf Hansson
(cherry picked from commit 5b67cd9c5ee0722022cba7d20552320325457434) -
Dereference the charger->psy after the power_supply is created to fix the
null pointer issue.Signed-off-by: Li Jun