08 Jun, 2017
40 commits
-
The two properties pm-ignore-notify and keep-power-in-suspend need
to remove for the sd slot on base board(sd1 slot).If not, after system suspend, once remove the card from sd1 slot,
then system can't resume successfully, resume process hung due to
dead lock.Signed-off-by: Haibo Chen
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Add reboot handler to send reboot message by rpmsg to M4 side, then
M4 will reboot A7 core. Meanwhile, remove shutdown interface at rpmsg
level, since M4 prefer to clear reboot and shutdown interface instead
of shutdown interface at rpmsg level.Signed-off-by: Robin Gong
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On i.mx7ulp, kernel need notify m4 side power mode message before enter VLLS
and resume back, but pm_qos_remove_request will enable local irq that cause
the below kernel warning since kernel assum local irq disalbed in syscore_resume.
In this case, just ignore touch pm_qos_* since cpu0 never enter idle at that
suspend time.WARNING: CPU: 0 PID: 629 at drivers/base/syscore.c:99 syscore_resume+0xcc/0xec()
Interrupts enabled before system core resume.
Modules linked in:
CPU: 0 PID: 629 Comm: sh Not tainted 4.1.33-02249-g69520ab-dirty #259
Hardware name: Freescale i.MX7ULP (Device Tree)
[] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[] (show_stack) from [] (dump_stack+0x88/0x9c)
[] (dump_stack) from [] (warn_slowpath_common+0x84/0xb4)
[] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
[] (warn_slowpath_fmt) from [] (syscore_resume+0xcc/0xec)
[] (syscore_resume) from [] (suspend_devices_and_enter+0x3c4/0x500)
[] (suspend_devices_and_enter) from [] (pm_suspend+0x280/0x2fcSigned-off-by: Robin Gong
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Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLKIMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.
Update copyright information.
Signed-off-by: Fugang Duan
Signed-off-by: Adrian Alonso -
Add one more dtb file for mfgtool purpose only, it enabled both eMMC and
QSPI to burn both BSP and M4 images in one process.Kernel still uses the original eMMC dtb so the QSPI, which belongs to
M4 domain won't be exposed in A7 domain.Signed-off-by: Han Xu
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Even though is not affecting the behaviour, the brackets are missing
to limit this check for imx6q as was intended in first placeSigned-off-by: Juan Gutierrez
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Correct this spelling mistake error for lpi2c5 node.
Signed-off-by: Fancy Fang
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Drop the VDD_SOC and VDD_ARM voltage to 0.9V when system runs at low
power run mode.Signed-off-by: Bai Ping
-
Add shutdown message to notify m4 side so that rpmsg can work
after A7 boot again.Signed-off-by: Robin Gong
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Alllign header format as M4 defined, no need revert order. Correct
the data to u8 instead of u32 as M4 defined. Call the header define
in imx_rpmsg.h derectly.Signed-off-by: Robin Gong
-
Add PM RPMSG for i.MX7ULP power management, currently
it handles heart beat function which will notify M4
that linux is alive every 30 seconds, and when system
enters/exit VLLS mode, it will notify M4 for proper
power management.Signed-off-by: Anson Huang
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On i.MX7ULP, add a new RPMSG instance for power management.
Signed-off-by: Anson Huang
-
For i.mx6q systems the mmdc handshake on channel 0 is kept enabled (while
channel 1 is bypassed). This is ok for lpddr2 systems operating on 1ch-mode,
but not true for 2ch-mode. On this case the handshake needs to be set for
both channels, otherwise a kernel panic or Oops error might be observed
after resuming from suspend.Signed-off-by: Juan Gutierrez
-
To configure the suspend settings for lpddr2 systems is necessary
to know if mmdc is operating on 1ch-mode or 2ch-mode.
Here, the imx_get_lpddr2_2ch_mode api is introduced to get this info
when needed and decide accordingly.Signed-off-by: Juan Gutierrez
-
The mmdc clk rate needs to be explicitly updated when moving to
high audio rate by the busfreq module for the i.mx6q lpddr2 systems.
In order to make the mmdc_ch0_axi clk visible by this driver, it
needs to be included on the clocks/clock-names list.For the imx6dqscm-1gb-evb systems the clocks list for the busfreq
module is originally inherited from imx6q.dtsi. To include the mmdc
clk, the full clocks list plus the mmdc clk needs to be overwriten
on the individual dts files.Signed-off-by: Juan Gutierrez
-
As periph_pre_clk's parent is not changed when going to high audio frequency,
the clk framework will not update its children's frequency. This cause
the the mmdc_ch0_axi clk_rate does not reflect the right frequency when
reading it from userspace like:cat /sys/kernel/debug/clk/mmdc_ch0_axi/clk_rate
Since the mmdc_ch0_axi_podf is changed in the asm busfreq routine, then the
mmdc rate needs to be updated to make sure clk tree is right, although it
will not do any change to hardware.To do this the clk_get_rate api is used to update the mmdc_clk which
needs to be dereferenced from the device tree. Since for other cases like
ddr3, the update of the rate of the mmdc clk is not needed, the absense of
this parameter (on the device tree) don't make throw an error, instead, NULL
checks are used to check if the mmdc clk needs to be updated or not.Signed-off-by: Juan Gutierrez
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After a frequency transition, like 400MHz to 24Mhz, on i.mx6DQ SCM
systems (which use lpddr2), the curr_ddr_rate variable retains its
previous cached value causing the next frequency update transition
to fail by following a wrong flow which results in a complete hang
of the system.Issuing an L1 cache flush during the freq update routine (as in in
MXSCM-241-1) and moving up the curr_ddr_rate variable before calling
tge freq update alleviates the problem.Signed-off-by: Juan Gutierrez
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Flush and disable L1 before disabling L2, to let data to be coherent.
Flushing L1 pushes everyhting to L2. L2 is sync later, but it can still
have dirty lines.Signed-off-by: Juan Gutierrez
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Changing tx-d-cal according to USB certification test results.
Signed-off-by: Peter Chen
-
Setting the xnur-gpio to GPIO_ACTIVE_LOW, otherwise touch calibration
may has some issue.Signed-off-by: Haibo Chen
-
The deadlock scenario is the following:
1. We schedule low_bus_freq_handle() but it does not run yet.
2. We run set_high_bus_freq() or some other function, that does the
following two things: (a) takes the busfreq mutex and (b)
synchronously cancel the low_bus_freq_handle workIf between (a) and (b) the low_bus_freq_handle work starts running, it
will take the bus freq mutex and block which will cause (b) to
deadlock since the work will never finish now.To fix this issue avoid synchronously canceling the work and instead
use a new global variable (protected by the busfreq mutex) to mark the
cancellation and abort the work when it is scheduled. In order to
avoid unnecessary schedules we also try to cancel the work with
cancel_delayed_work().======================================================
[ INFO: possible circular locking dependency detected ]
4.9.0-rc4-00776-gd4f2779 #348 Tainted: G W
-------------------------------------------------------
kworker/3:1/68 is trying to acquire lock:
(
bus_freq_mutex
){+.+...}
, at:
[] reduce_bus_freq_handler+0x1c/0x30but task is already holding lock:
(
(&(&low_bus_freq_handler)->work)
){+.+...}
, at:
[] process_one_work+0x128/0x418which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:
-> #1
(
(&(&low_bus_freq_handler)->work)
){+.+...}
:[] flush_work+0x44/0x234
[] __cancel_work_timer+0x98/0x1c8
[] cancel_delayed_work_sync+0x14/0x18
[] request_bus_freq+0x9c/0x150
[] imx6q_cpufreq_init+0x8c/0xb8
[] cpufreq_online+0xc0/0x67c
[] cpufreq_add_dev+0xb0/0xd4
[] subsys_interface_register+0x9c/0xd8
[] cpufreq_register_driver+0x130/0x1dc
[] imx6q_cpufreq_probe+0x5c8/0x8a0
[] platform_drv_probe+0x54/0xb8
[] driver_probe_device+0x20c/0x2c4
[] __device_attach_driver+0x9c/0xb4
[] bus_for_each_drv+0x6c/0xa0
[] __device_attach+0xb8/0x11c
[] device_initial_probe+0x14/0x18
[] bus_probe_device+0x90/0x98
[] device_add+0x3c8/0x578
[] platform_device_add+0xa8/0x208
[] platform_device_register+0x28/0x2c
[] imx6q_init_late+0x180/0x1c8
[] init_machine_late+0x24/0x98
[] do_one_initcall+0x44/0x180
[] kernel_init_freeable+0x12c/0x1f4
[] kernel_init+0x10/0x120
[] ret_from_fork+0x14/0x24-> #0
(
bus_freq_mutex
){+.+...}
:[] lock_acquire+0x78/0x98
[] mutex_lock_nested+0x54/0x3e4
[] reduce_bus_freq_handler+0x1c/0x30
[] process_one_work+0x194/0x418
[] worker_thread+0x34/0x4fc
[] kthread+0xdc/0xf8
[] ret_from_fork+0x14/0x24other info that might help us debug this:
Possible unsafe locking scenario:
CPU0 CPU1
---- ----
lock( (&(&low_bus_freq_handler)->work) );
lock( bus_freq_mutex );
lock( (&(&low_bus_freq_handler)->work) );
lock( bus_freq_mutex );*** DEADLOCK ***
2 locks held by kworker/3:1/68:
#0:
(
"events"
){.+.+.+}
, at:
[] process_one_work+0x128/0x418
#1:
(
(&(&low_bus_freq_handler)->work)
){+.+...}
, at:
[] process_one_work+0x128/0x418stack backtrace:
CPU: 3 PID: 68 Comm: kworker/3:1 Tainted: G W 4.9.0-rc4-00776-gd4f2779 #348
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
Workqueue: events reduce_bus_freq_handler
Backtrace:
[] (dump_backtrace) from [] (show_stack+0x18/0x1c)
[] (show_stack) from [] (dump_stack+0xb4/0xe8)
[] (dump_stack) from [] (print_circular_bug+0x1d4/0x318)
[] (print_circular_bug) from [] (__lock_acquire+0x1864/0x1ad4)
[] (__lock_acquire) from [] (lock_acquire+0x78/0x98)
[] (lock_acquire) from [] (mutex_lock_nested+0x54/0x3e4)
[] (mutex_lock_nested) from [] (reduce_bus_freq_handler+0x1c/0x30)
[] (reduce_bus_freq_handler) from [] (process_one_work+0x194/0x418)
[] (process_one_work) from [] (worker_thread+0x34/0x4fc)
[] (worker_thread) from [] (kthread+0xdc/0xf8)
[] (kthread) from [] (ret_from_fork+0x14/0x24)Signed-off-by: Octavian Purdila
Reviewed-by: Ranjani Vaidyanathan -
Fix busfreq support on i.MX6ULL LPDDR2 board.
Signed-off-by: Bai Ping
-
Setting the xnur-gpio to GPIO_ACTIVE_LOW, otherwise touch calibration
may has some issue.Signed-off-by: Haibo Chen
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Add ocotp node.
Signed-off-by: Peng Fan
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Add ldo enable dts
Signed-off-by: Robin Gong
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The iomux PAD setting for QSPI on i.MX7ULP should belong to
iomuxc0(refers to iomuxc in dtsi file) rather than iomuxc1.Signed-off-by: Han Xu
-
Below error happen when boot up imx6ul/imx6ull 9x9 board. which is caused by
that dts is not updated in commit 0a4c5844f91de8 ("MLK-12059 ARM: dts:
imx6ul-14x14-evk: add mic detect gpio to support headset Jack")[ 1.871240] imx-wm8960 sound: ASoC: Failed to add route HP_L -> direct -> Headset Jack
[ 1.884002] imx-wm8960 sound: ASoC: Failed to add route HP_R -> direct -> Headset Jack
[ 1.896532] imx-wm8960 sound: ASoC: Failed to add route Hp MIC -> direct -> LINPUT2
[ 1.909936] imx-wm8960 sound: ASoC: Failed to add route Hp MIC -> direct -> LINPUT3
[ 1.923511] imx-wm8960 sound: ASoC: Failed to add route MICB -> direct -> Hp MICSigned-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
Add modem gpio reset for lpuart6 port.
Signed-off-by: Fugang Duan
-
The untrimmed chip firc clock is 50Mhz after manually tuning.
Now the trimmed chip firc clock is stable to 48Mhz, so change
the lpuart module clock rate to 48Mhz.Signed-off-by: Fugang Duan
-
Because i.mx6sll support mega_fast power off, sdma driver can sync
with i.mx6ul which support this feature. Modify compatible nameSigned-off-by: Robin Gong
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set the baseAddress with 0x10000000 on IMX6Q
Signed-off-by: Yuchou Gan
Date: Jan 10, 2017 -
add imx7d pcie phy node into 7d dts
Signed-off-by: Richard Zhu
-
input the vring buffer by device tree node, and
remove the hard-coded vring buffer in the driverSigned-off-by: Richard Zhu
-
In order to remove the hard-coded vring buffer in
the driver, input the vring buffer by device tree
node.Signed-off-by: Richard Zhu
-
The vbus should be output, and the id should be input.
Without this change, the GPIO configuration (through pinctrl
register) is incorrect from system suspend.Signed-off-by: Peter Chen
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At imx7ulp VLLS mode, the power of iomux1 is lost, so we need to
recover pinctrl value when back from this mode.Signed-off-by: Peter Chen
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Add lpspi sleep pinctrl.
Signed-off-by: Gao Pan
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Add lpi2c sleep pinctrl.
Signed-off-by: Gao Pan
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Add 'FB_MXC_OVERLAY' config to control overlay framebuffer
feature. And also add this config to defconfig.Signed-off-by: Fancy Fang
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Add lpuart sleep pinctrl.
Signed-off-by: Fugang Duan