Eric Lee / smarc-fsl-linux-kernel

10 Oct, 2018

1 commit

02 Oct, 2018

1 commit

29 Aug, 2018

1 commit

27 Jul, 2018

1 commit

05 Jun, 2018

1 commit

  • 218d72a77   pinctrl: madera: Add driver for Cirrus Logic Madera codecs ... Browse Code »

    These codecs have a variable number of I/O lines each of which
    is individually selectable to a wide range of possible functions.

    The functionality is slightly different from the traditional muxed
    GPIO since most of the functions can be mapped to any pin (and even
    the same function to multiple pins). Most pins have a dedicated
    "alternate" function that is only available on that pin. The
    alternate functions are usually a group of signals, though it is
    not always necessary to enable the full group, depending on the
    alternate function and how it is to be used. The mapping between
    alternate functions and GPIO pins varies between codecs depending
    on the number of alternate functions and available pins.

    Signed-off-by: Richard Fitzgerald
    Reviewed-by: Linus Walleij
    Signed-off-by: Lee Jones

    Richard Fitzgerald
     

02 May, 2018

1 commit

  • 2242ddfbf   pinctrl: actions: Add Actions S900 pinctrl driver ... Browse Code »

    Add pinctrl driver for Actions Semi S900 SoC. The driver supports
    pinctrl, pinmux and pinconf functionalities through a range of registers
    common to both gpio driver and pinctrl driver.

    Pinmux functionality is available only for the pin groups while the
    pinconf functionality is available for both pin groups and individual
    pins.

    Signed-off-by: Manivannan Sadhasivam
    Signed-off-by: Linus Walleij

    Manivannan Sadhasivam
     

04 Apr, 2018

1 commit

  • 77624cd2a   Merge tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl ... Browse Code »

    Pull pin control bulk updates from Linus Walleij:
    "New drivers:

    - Qualcomm SDM845: this is their new flagship SoC platform which
    seems to be targeted at premium mobile handsets.

    - Renesas R-Car M3-N SoC.

    - Renesas R8A77980 SoC.

    - NXP (ex Freescale) i.MX 6SLL SoC.

    - Mediatek MT2712 SoC.

    - Allwinner H6 SoC.

    Improvements:

    - Uniphier adds a few new functions and pins.

    - Renesas refactorings and additional pin definitions.

    - Improved pin groups for Axis Artpec6.

    Cleanup:

    - Drop the TZ1090 drivers. This platform is no longer maintained and
    is being deleted.

    - Drop ST-Ericsson U8540/U9540 support as this was never
    productified.

    - Overall minor fixes and janitorial"

    * tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
    pinctrl: uniphier: add UART hardware flow control pin-mux settings
    pinctrl: sunxi: add support for the Allwinner H6 main pin controller
    pinctrl: sunxi: change irq_bank_base to irq_bank_map
    pinctrl: sunxi: introduce IRQ bank conversion function
    pinctrl: sunxi: refactor irq related register function to have desc
    pinctrl: msm8998: Remove owner assignment from platform_driver
    pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group
    pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings
    pinctrl/amd: poll InterruptEnable bits in enable_irq
    pinctrl: ocelot: fix gpio direction
    pinctrl: mtk: fix check warnings.
    pintcrl: mtk: support bias-disable of generic and special pins simultaneously
    pinctrl: add mt2712 pinctrl driver
    pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0
    pinctrl: imx: Add pinctrl driver support for imx6sll
    dt-bindings: imx: update pinctrl doc for imx6sll
    pinctrl: intel: Implement intel_gpio_get_direction callback
    pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependency
    pinctrl: mediatek: mtk-common: use true and false for boolean values
    pinctrl: sunxi: always look for apb block
    ...

    Linus Torvalds
     

26 Mar, 2018

1 commit

01 Mar, 2018

1 commit

  • 4a7cba71c   pinctrl: Drop TZ1090 drivers ... Browse Code »

    Now that arch/metag/ has been removed, along with TZ1090 SoC support,
    remove the TZ1090 pinctrl drivers. They are of no value without the
    architecture and SoC platform code.

    Signed-off-by: James Hogan
    Cc: linux-gpio@vger.kernel.org
    Cc: linux-metag@vger.kernel.org
    Signed-off-by: Linus Walleij

    James Hogan
     

09 Jan, 2018

1 commit

20 Dec, 2017

1 commit

  • d6ed93551   pinctrl: mediatek: add pinctrl driver for MT7622 SoC ... Browse Code »

    Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has
    the registers for pinctrl, pinconf and gpio mixed up in the same register
    range. However, the IO core for the MT7622 SoC is completely distinct from
    anyone of previous MediaTek SoCs which already had support, such as
    the hardware internal, register address map and register detailed
    definition for each pin.

    Therefore, instead, the driver is being newly implemented by reusing
    generic methods provided from the core layer with GENERIC_PINCONF,
    GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code
    simplicity and rid of superfluous code. Where the function of pins
    determined by groups is utilized in this driver which can help developers
    less confused with what combinations of pins effective on the SoC and even
    reducing the mistakes during the integration of those relevant boards.

    As the gpio_chip handling is also only a few lines, the driver also
    implements the gpio functionality directly through GPIOLIB.

    Signed-off-by: Sean Wang
    Reviewed-by: Biao Huang
    Signed-off-by: Linus Walleij

    Sean Wang
     

07 Dec, 2017

1 commit

02 Nov, 2017

1 commit

  • b24413180   License cleanup: add SPDX GPL-2.0 license identifier to files with no license ... Browse Code »

    Many source files in the tree are missing licensing information, which
    makes it harder for compliance tools to determine the correct license.

    By default all files without license information are under the default
    license of the kernel, which is GPL version 2.

    Update the files which contain no license information with the 'GPL-2.0'
    SPDX license identifier. The SPDX identifier is a legally binding
    shorthand, which can be used instead of the full boiler plate text.

    This patch is based on work done by Thomas Gleixner and Kate Stewart and
    Philippe Ombredanne.

    How this work was done:

    Patches were generated and checked against linux-4.14-rc6 for a subset of
    the use cases:
    - file had no licensing information it it.
    - file was a */uapi/* one with no licensing information in it,
    - file was a */uapi/* one with existing licensing information,

    Further patches will be generated in subsequent months to fix up cases
    where non-standard license headers were used, and references to license
    had to be inferred by heuristics based on keywords.

    The analysis to determine which SPDX License Identifier to be applied to
    a file was done in a spreadsheet of side by side results from of the
    output of two independent scanners (ScanCode & Windriver) producing SPDX
    tag:value files created by Philippe Ombredanne. Philippe prepared the
    base worksheet, and did an initial spot review of a few 1000 files.

    The 4.13 kernel was the starting point of the analysis with 60,537 files
    assessed. Kate Stewart did a file by file comparison of the scanner
    results in the spreadsheet to determine which SPDX license identifier(s)
    to be applied to the file. She confirmed any determination that was not
    immediately clear with lawyers working with the Linux Foundation.

    Criteria used to select files for SPDX license identifier tagging was:
    - Files considered eligible had to be source code files.
    - Make and config files were included as candidates if they contained >5
    lines of source
    - File already had some variant of a license header in it (even if
    Reviewed-by: Philippe Ombredanne
    Reviewed-by: Thomas Gleixner
    Signed-off-by: Greg Kroah-Hartman

    Greg Kroah-Hartman
     

08 Sep, 2017

1 commit

  • 968c61f7d   Merge tag 'mfd-next-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd ... Browse Code »

    Pull MFD updates from Lee Jones:
    "New Drivers
    - RK805 Power Management IC (PMIC)
    - ROHM BD9571MWV-M MFD Power Management IC (PMIC)
    - Texas Instruments TPS68470 Power Management IC (PMIC) & LEDs

    New Device Support:
    - Add support for HiSilicon Hi6421v530 to hi6421-pmic-core
    - Add support for X-Powers AXP806 to axp20x
    - Add support for X-Powers AXP813 to axp20x
    - Add support for Intel Sunrise Point LPSS to intel-lpss-pci

    New Functionality:
    - Amend API to provide register layout; atmel-smc

    Fix-ups:
    - DT re-work; omap, nokia
    - Header file location change {I2C => MFD}; dm355evm_msp, tps65010
    - Fix chip ID formatting issue(s); rk808
    - Optionally register touchscreen devices; da9052-core
    - Documentation improvements; twl-core
    - Constification; rtsx_pcr, ab8500-core, da9055-i2c, da9052-spi
    - Drop unnecessary static declaration; max8925-i2c
    - Kconfig changes (missing deps and remove module support)
    - Slim down oversized licence statement; hi6421-pmic-core
    - Use managed resources (devm_*); lp87565
    - Supply proper error checking/handling; t7l66xb

    Bug Fixes:
    - Fix counter duplication issue; da9052-core
    - Fix potential NULL deference issue; max8998
    - Leave SPI-NOR write-protection bit alone; lpc_ich
    - Ensure device is put into reset during suspend; intel-lpss
    - Correct register offset variable size; omap-usb-tll"

    * tag 'mfd-next-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (61 commits)
    mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants
    mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT
    dt-bindings: mfd: Add bindings for ZII RAVE devices
    mfd: omap-usb-tll: Fix register offsets
    mfd: da9052: Constify spi_device_id
    mfd: intel-lpss: Put I2C and SPI controllers into reset state on suspend
    mfd: da9055: Constify i2c_device_id
    mfd: intel-lpss: Add missing PCI ID for Intel Sunrise Point LPSS devices
    mfd: t7l66xb: Handle return value of clk_prepare_enable
    mfd: Add ROHM BD9571MWV-M PMIC DT bindings
    mfd: intel_soc_pmic_chtwc: Turn Kconfig option into a bool
    mfd: lp87565: Convert to use devm_mfd_add_devices()
    mfd: Add support for TPS68470 device
    mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell
    mfd: syscon: atmel-smc: Add helper to retrieve register layout
    mfd: axp20x: Use correct platform device ID for many PEK
    dt-bindings: mfd: axp20x: Introduce bindings for AXP813
    mfd: axp20x: Add support for AXP813 PMIC
    dt-bindings: mfd: axp20x: Add AXP806 to supported list of chips
    mfd: Add ROHM BD9571MWV-M MFD PMIC driver
    ...

    Linus Torvalds
     

31 Aug, 2017

1 commit

21 Aug, 2017

1 commit

  • ea479996c   pinctrl: Add pinctrl driver for the RK805 PMIC ... Browse Code »

    RK805 is one of Rockchip PMICs family, it has 2 output only GPIOs.

    This driver is also designed for other Rockchip PMICs to expend.
    Different PMIC maybe have different pin features, for example,
    RK816 has one pin which can be used for TS or GPIO(input/out).
    The mainly difference between PMICs pins are pinmux, direction
    and output value, that is 'struct rk805_pin_config'.

    Signed-off-by: Joseph Chen
    Acked-by: Linus Walleij
    Signed-off-by: Heiko Stuebner
    Signed-off-by: Lee Jones

    Joseph Chen
     

14 Aug, 2017

1 commit

  • 06351d133   pinctrl: add a Gemini SoC pin controller ... Browse Code »

    This adds a pin control (only multiplexing) driver for the Gemini
    SoC so we can sort out this complex platform in an orderly manner.

    This driver will detect the chip/package version as SL3512 or SL3516
    (also known as CS3512 and CS3516 etc) and register the apropriate
    pin set.

    Signed-off-by: Linus Walleij

    Linus Walleij
     

29 Jun, 2017

1 commit

23 Jun, 2017

1 commit

23 May, 2017

2 commits

22 May, 2017

3 commits

  • bdb18d93a   Merge branch 'ingenic' into devel Browse Code »
    Linus Walleij
     
  • b5c23aa46   pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs ... Browse Code »

    This driver handles pin configuration and pin muxing for the
    JZ4740 and JZ4780 SoCs from Ingenic.

    Signed-off-by: Paul Cercueil
    Signed-off-by: Linus Walleij

    Paul Cercueil
     
  • cbff0c4d2   pinctrl: add ZTE ZX pinctrl driver support ... Browse Code »

    The pin controller on ZTE ZX platforms is kinda of hybrid. It consists
    of a main controller and an auxiliary one. For example, on ZX296718 SoC,
    the main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both
    controllers work together to control pin multiplexing and configuration.

    For most of pins, the pinmux function is controlled by main controller
    only, and this type of pins are meant by term 'TOP pins'. For other
    pins, the pinmux is controlled by both main and auxiliary controllers,
    as the available multiplexing functions for the pin spread in both
    controllers. This type of pins are called 'AON pins'. Though pinmux
    implementation is quite different, pinconf is same for both types of
    pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG on
    ZX296718.

    The patch adds the ZTE ZX core pinctrl driver to support this hybrid
    pin controller as well as ZX296718 SoC specific pin data.

    Signed-off-by: Shawn Guo
    Signed-off-by: Linus Walleij

    Shawn Guo
     

24 Apr, 2017

1 commit

  • 87466ccd9   pinctrl: armada-37xx: Add pin controller support for Armada 37xx ... Browse Code »

    The Armada 37xx SoC come with 2 pin controllers: one on the south
    bridge (managing 28 pins) and one on the north bridge (managing 36 pins).

    At the hardware level the controller configure the pins by group and not
    pin by pin. This constraint is reflected in the design of the driver:
    only the group related functions are implemented.

    Signed-off-by: Gregory CLEMENT
    Signed-off-by: Linus Walleij

    Gregory CLEMENT
     

07 Apr, 2017

1 commit

  • 00df0582e   pinctrl: Add pincontrol driver for ARTPEC-6 SoC ... Browse Code »

    Add pinctrl driver support for the Axis ARTPEC-6 SoC.
    There are only some pins that actually have different
    functions available, but all can control bias (pull-up/-down)
    and drive strength.

    Code originally written by Chris Paterson.

    Signed-off-by: Jesper Nilsson
    Signed-off-by: Linus Walleij

    Jesper Nilsson
     

10 Jan, 2017

1 commit

  • 003910ebc   pinctrl: Introduce TI IOdelay configuration driver ... Browse Code »

    SoC family such as DRA7 family of processors have, in addition
    to the regular muxing of pins (as done by pinctrl-single), a separate
    hardware module called IODelay which is also expected to be configured.
    The "IODelay" module has it's own register space that is independent
    of the control module and the padconf register area.

    With recent changes to the pinctrl framework, we can now support
    this hardware with a reasonably minimal driver by using #pinctrl-cells,
    GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS.

    It is advocated strongly in TI's official documentation considering
    the existing design of the DRA7 family of processors during mux or
    IODelay reconfiguration, there is a potential for a significant glitch
    which may cause functional impairment to certain hardware. It is
    hence recommended to do as little of muxing as absolutely necessary
    without I/O isolation (which can only be done in initial stages of
    bootloader).

    NOTE: with the system wide I/O isolation scheme present in DRA7 SoC
    family, it is not reasonable to do stop all I/O operations for every
    such pad configuration scheme. So, we will let it glitch when used in
    this mode.

    Even with the above limitation, certain functionality such as MMC has
    mandatory need for IODelay reconfiguration requirements, depending on
    speed of transfer. In these cases, with careful examination of usecase
    involved, the expected glitch can be controlled such that it does not
    impact functionality.

    In short, IODelay module support as a padconf driver being introduced
    here is not expected to do SoC wide I/O Isolation and is meant for
    a limited subset of IODelay configuration requirements that need to
    be dynamic and whose glitchy behavior will not cause functionality
    failure for that interface.

    IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared
    to 0x0 at all times, even when configuring Manual IO Timing Modes.
    This is done by eliminating the LOCK_BIT=1 setting from Step
    of the Manual IO timing Mode configuration procedure. This option
    leaves the CFG_* registers unprotected from unintended writes to the
    CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured.

    This approach is taken to allow for a generic driver to exist in kernel
    world that has to be used carefully in required usecases.

    Signed-off-by: Nishanth Menon
    Signed-off-by: Lokesh Vutla
    [tony@atomide.com: updated to use generic pinctrl functions, added
    binding documentation, updated comments]
    Acked-by: Rob Herring
    Signed-off-by: Tony Lindgren
    Signed-off-by: Linus Walleij

    Nishanth Menon
     

07 Dec, 2016

1 commit

24 Oct, 2016

1 commit

  • 9e80f9064   pinctrl: Add SX150X GPIO Extender Pinctrl Driver ... Browse Code »

    Since the I2C sx150x GPIO expander driver uses platform_data to manage
    the pins configurations, rewrite the driver as a pinctrl driver using
    pinconf to get/set pin configurations from DT or debugfs.

    The pinctrl driver is functionnally equivalent as the gpio-only driver
    and can use DT for pinconf. The platform_data confirmation is dropped.

    This patchset removed the gpio-only driver and selects the Pinctrl driver
    config instead. This patchset also migrates the gpio dt-bindings to pinctrl
    and add the pinctrl optional properties.

    The driver was tested with a SX1509 device on a BeagleBone black with
    interrupt support and on an X86_64 machine over an I2C to USB converter.

    This is a fixed version that builds and runs on non-OF platforms and on
    arm based OF. The GPIO version is removed and the bindings are also moved
    to the pinctrl bindings.

    Changes since v2
    - rebased on v4.9-rc1
    - removed MODULE_DEVICE_TABLE as in upstream bb411e771b0e
    ("gpio: sx150x: fix implicit assumption module.h is present")

    Changes since v1
    - Fix Kconfig descriptions on pinctrl and gpio
    - Fix Kconfig dependency
    - Remove oscio support for non-789 devices
    - correct typo in dt bindings
    - remove probe reset for non-789 devices

    Changes since RFC
    - Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms
    - No more rely on OF_GPIO config
    - Moved and enhanced bindings to pinctrl bindings
    - Removed gpio-sx150x.c
    - Temporary select PINCTRL_SX150X when GPIO_SX150X
    - Temporary mark GPIO_SX150X as deprecated

    Signed-off-by: Neil Armstrong
    Tested-by: Peter Rosin
    Acked-by: Rob Herring
    ested-by: Andrey Smirnov
    Signed-off-by: Linus Walleij

    Neil Armstrong
     

07 Sep, 2016

1 commit

  • 4d3d0e427   pinctrl: Add core support for Aspeed SoCs ... Browse Code »

    The Aspeed SoCs typically provide more than 200 pins for GPIO and other
    functions. The signal enabled on a pin is determined on a priority
    basis, where a given pin can provide a number of different signal types.

    In addition to the priority levels, the Aspeed pin controllers describe
    the signal active on a pin by compound logical expressions involving
    multiple operators, registers and bits. Some difficulty arises as a
    pin's function bit masks for each priority level are frequently not the
    same (i.e. we cannot just flip a bit to change from a high to low
    priority signal), or even in the same register(s). Some configuration
    bits affect multiple pins, while in other cases the signals for a bus
    must each be enabled individually.

    Together, these features give rise to some complexity in the
    implementation. A more complete description of the complexities is
    provided in the associated header file.

    The patch doesn't implement pinctrl/pinmux/pinconf for any particular
    Aspeed SoC, rather it adds the framework for defining pinmux
    configurations.

    Signed-off-by: Andrew Jeffery
    Reviewed-by: Joel Stanley
    Signed-off-by: Linus Walleij

    Andrew Jeffery
     

29 Jul, 2016

1 commit

  • d94ba9e7d   Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl ... Browse Code »

    Pull pin control updates from Linus Walleij:
    "This is the bulk of pin control changes for the v4.8 kernel cycle.

    Nothing stands out as especially exiting: new drivers, new subdrivers,
    lots of cleanups and incremental features.

    Business as usual.

    New drivers:

    - New driver for Oxnas pin control and GPIO. This ARM-based chipset
    is used in a few storage (NAS) type devices.

    - New driver for the MAX77620/MAX20024 pin controller portions.

    - New driver for the Intel Merrifield pin controller.

    New subdrivers:

    - New subdriver for the Qualcomm MDM9615

    - New subdriver for the STM32F746 MCU

    - New subdriver for the Broadcom NSP SoC.

    Cleanups:

    - Demodularization of bool compiled-in drivers.

    Apart from this there is just regular incremental improvements to a
    lot of drivers, especially Uniphier and PFC"

    * tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
    pinctrl: fix pincontrol definition for marvell
    pinctrl: xway: fix typo
    Revert "pinctrl: amd: make it explicitly non-modular"
    pinctrl: iproc: Add NSP and Stingray GPIO support
    pinctrl: Update iProc GPIO DT bindings
    pinctrl: bcm: add OF dependencies
    pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
    pinctrl: Add STM32F746 MCU support
    pinctrl: intel: Protect set wake flow by spin lock
    pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
    pinctrl: uniphier: add Ethernet pin-mux settings
    sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
    pinctrl: ns2: fix return value check in ns2_pinmux_probe()
    pinctrl: qcom: update DT bindings with ebi2 groups
    pinctrl: qcom: establish proper EBI2 pin groups
    pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
    Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
    includes: dt-bindings: Add STM32F746 pinctrl DT bindings
    pinctrl: sunxi: fix nand0 function name for sun8i
    pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
    ...

    Linus Torvalds
     

22 Jun, 2016

1 commit

  • 19b5a9176   pinctrl: tegra: Fix build dependency ... Browse Code »

    I got below build error:
    ERROR: "tegra_xusb_padctl_legacy_probe"
    [drivers/phy/tegra/phy-tegra-xusb.ko] undefined!
    with below build configuration:
    CONFIG_ARCH_TEGRA=y
    CONFIG_PINCTRL_TEGRA_XUSB=y
    CONFIG_PHY_TEGRA_XUSB=y

    The problem is below line in drivers/pinctrl/Makefile
    obj-$(CONFIG_PINCTRL_TEGRA) += tegra/

    So even CONFIG_PINCTRL_TEGRA_XUSB=y is set, kbuild still does not compile
    the code in drivers/pinctrl/tegra folder if !CONFIG_PINCTRL_TEGRA.

    phy-tegra-xusb.c does not use any symbol from pinctrl-tegra.c,
    so build pinctrl-tegra.c only when CONFIG_PINCTRL_TEGRA is set.

    Signed-off-by: Axel Lin
    Acked-by: Jon Hunter
    Signed-off-by: Linus Walleij

    Axel Lin
     

13 Jun, 2016

1 commit

  • f886031f6   pinctrl: Always recurse into bcm folder ... Browse Code »

    drivers/pinctrl/bcm/Makefile properly builds individual drivers based on
    their respective Kconfig symbols. ARCH_BCM is currently a menuconfig
    option from arch/arm/mach-bcm/Kconfig, which is fine, but prevents ARM64
    platforms which do not have such menuconfig option from building their
    pinctrl drivers, so let's get rid of that dependency.

    Signed-off-by: Florian Fainelli
    Acked-by: Scott Branden
    Acked-by: Eric Anholt
    Signed-off-by: Linus Walleij

    Florian Fainelli
     

30 May, 2016

2 commits

14 Feb, 2016

1 commit

09 Feb, 2016

1 commit

  • 4afe26845   pinctrl: stm32: Fix compile testing selection ... Browse Code »

    While selecting the driver for compile testing seemed possible,
    the driver was not compiled because the driver directory was only
    added if ARCH_STM32 was selected.

    This patch now makes the pinctrl Makefile to add stm32 directory if
    PINCTRL_STM32 is selected.

    Signed-off-by: Maxime Coquelin
    Signed-off-by: Linus Walleij

    Maxime Coquelin
     

06 Feb, 2016

1 commit

  • 2ba384e6c   pinctrl: pinctrl-pic32: Add PIC32 pin control driver ... Browse Code »

    Add a driver for the pin controller present on the Microchip PIC32
    including the specific variant PIC32MZDA. This driver provides pinmux
    and pinconfig operations as well as GPIO and IRQ chips for the GPIO
    banks.

    Signed-off-by: Joshua Henderson
    Cc: Ralf Baechle
    Cc: Linus Walleij
    Signed-off-by: Linus Walleij

    Joshua Henderson
     

05 Feb, 2016

1 commit

28 Jan, 2016

1 commit