Eric Lee / smarc-fsl-linux-kernel

29 Sep, 2015

1 commit

  • ccc42592d   clocksource/drivers/rockchip: Fix bad NO_IRQ usage ... Browse Code »

    The current code assumes the 'irq_of_parse_and_map' will return NO_IRQ in case
    of failure. Unfortunately, the NO_IRQ is not consistent across the different
    architectures and we must not rely on it.

    NO_IRQ is equal to '-1' on ARM and 'irq_of_parse_and_map' returns '0' in case
    of an error. Hence, the latter won't be detected and will lead to a crash.

    Fix this by just checking 'irq' is different from zero.

    Signed-off-by: Daniel Lezcano

    Daniel Lezcano
     

10 Aug, 2015

1 commit

  • 99b3fa72e   clockevents/drivers/rockchip: Migrate to new 'set-state' interface ... Browse Code »

    Migrate rockchip driver to the new 'set-state' interface provided by
    clockevents core, the earlier 'set-mode' interface is marked obsolete
    now.

    This also enables us to implement callbacks for new states of clockevent
    devices, for example: ONESHOT_STOPPED.

    We weren't doing anything for oneshot or resume modes, and so the
    callbacks aren't provided.

    Cc: Heiko Stuebner
    Signed-off-by: Viresh Kumar
    Signed-off-by: Daniel Lezcano

    Viresh Kumar
     

29 Jan, 2015

1 commit

  • 468b8c4cf   clockevents: rockchip: Add rockchip timer for rk3288 ... Browse Code »

    The rk3288 board uses the architected timers and these ones are shutdown when
    the cpu is powered down. There is a need of a broadcast timer in this case to
    ensure proper wakeup when the cpus are in sleep mode and a timer expires.

    This driver provides the basic timer functionnality as a backup for the local
    timers at sleep time.

    The timer belongs to the alive subsystem. It includes two programmables 64 bits
    timer channels but the driver only uses 32bits. It works with two operations
    mode: free running and user defined count.

    Programing sequence:

    1. Timer initialization:
    * Disable the timer by writing '0' to the CONTROLREG register
    * Program the timer mode by writing the mode to the CONTROLREG register
    * Set the interrupt mask

    2. Setting the count value:
    * Load the count value to the registers COUNT0 and COUNT1 (not used).

    3. Enable the timer
    * Write '1' to the CONTROLREG register with the mode (free running or user)

    Signed-off-by: Daniel Lezcano
    Reviewed-by: Heiko Stuebner

    Daniel Lezcano