12 Nov, 2020
1 commit
-
Add USB PHY parameters tuning for USB certifications.
Reviewed-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit 4fee6f2d570373d53d83e2c1c76cf8b40326d20a)
26 Oct, 2020
1 commit
-
Since the bug had been fixed on A1 chip and A0 chip is not supported
anymore, so remove the SW workaround.
NOTE: PCIe wouldn't work anymore on A0 chip after the SW workatound is
removed.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
08 Oct, 2020
1 commit
-
* tag 'v5.4.70': (3051 commits)
Linux 5.4.70
netfilter: ctnetlink: add a range check for l3/l4 protonum
ep_create_wakeup_source(): dentry name can change under you...
...Conflicts:
arch/arm/mach-imx/pm-imx6.c
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
drivers/crypto/caam/caamalg.c
drivers/gpu/drm/imx/dw_hdmi-imx.c
drivers/gpu/drm/imx/imx-ldb.c
drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c
drivers/mmc/host/sdhci-esdhc-imx.c
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
drivers/net/ethernet/freescale/enetc/enetc.c
drivers/net/ethernet/freescale/enetc/enetc_pf.c
drivers/thermal/imx_thermal.c
drivers/usb/cdns3/ep0.c
drivers/xen/swiotlb-xen.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.cSigned-off-by: Jason Liu
07 Oct, 2020
1 commit
-
[ Upstream commit 850280156f6421a404f2351bee07a0e7bedfd4c6 ]
If devm_phy_create() fails then we need to call of_clk_del_provider(node)
to undo the call to of_clk_add_provider().Fixes: 71e2f5c5c224 ("phy: ti: Add a new SERDES driver for TI's AM654x SoC")
Signed-off-by: Dan Carpenter
Link: https://lore.kernel.org/r/20200905124648.GA183976@mwanda
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin
01 Oct, 2020
1 commit
-
[ Upstream commit 05942b8c36c7eb5d3fc5e375d4b0d0c49562e85d ]
The USB phy takes some time to reset, so make sure we give it to it. The
delay length was taken from the 4x12 phy driver.This manifested in issues with the DWC2 driver since commit fe369e1826b3
("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.")
where the endianness check would read the DWC ID as 0 due to the phy still
resetting, resulting in the wrong endian mode being chosen.Signed-off-by: Jonathan Bakker
Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.com
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
17 Sep, 2020
1 commit
-
commit afd55e6d1bd35b4b36847869011447a83a81c8e0 upstream.
There were some problem in ipq8074 Gen2 PCIe phy init sequence.
1. Few register values were wrongly updated in the phy init sequence.
2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter
register which is added in serdes table causing the wrong register
was getting updated.
3. Clocks and resets were not added in the phy init.Fix these to make Gen2 PCIe port on ipq8074 devices to work.
Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074")
Cc: stable@vger.kernel.org
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
Link: https://lore.kernel.org/r/1596036607-11877-4-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Vinod Koul
Signed-off-by: Greg Kroah-Hartman
21 Aug, 2020
1 commit
-
usb phy with charger detection as power supply consumer can't
hold power supply use count when there is no interaction with it,
otherwise, if we unregister the power supply provider, there will
be kernel warning, to resolve this, we put the power supply after
use it.Reviewed-by: Peter Chen
Signed-off-by: Li Jun
20 Aug, 2020
1 commit
-
imx8mq and imx8mp USB PHY have battery charging detection function,
do it when set phy mode for usb device as this should be done before
host start enumeration. Link the detection result to power supply
(e.g. typec port manager).Reviewed-by: Peter Chen
Signed-off-by: Li Jun
19 Aug, 2020
3 commits
-
[ Upstream commit 1dea06cd643da38931382ebdc151efced201ffad ]
The mvneta hardware appears to lock up in various random ways when
repeatedly switching speeds between 1G and 2.5G, which involves
reprogramming the COMPHY. It is not entirely clear why this happens,
but best guess is that reprogramming the COMPHY glitches mvneta clocks
causing the hardware to fail. It seems that rebooting resolves the
failure, but not down/up cycling the interface alone.Various other approaches have been tried, such as trying to cleanly
power down the COMPHY and then take it back through the power up
initialisation, but this does not seem to help.It was finally noticed that u-boot's last step when configuring a
COMPHY for "SGMII" mode was to poke at a register described as
"GBE_CONFIGURATION_REG", which is undocumented in any external
documentation. All that we have is the fact that u-boot sets a bit
corresponding to the "SGMII" lane at the end of COMPHY initialisation.Experimentation shows that if we clear this bit prior to changing the
speed, and then set it afterwards, mvneta does not suffer this problem
on the SolidRun Clearfog when switching speeds between 1G and 2.5G.This problem was found while script-testing phylink.
This fix also requires the corresponding change to DT to be effective.
See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching
speeds".Fixes: 14dc100b4411 ("phy: armada38x: add common phy support")
Signed-off-by: Russell King
Reviewed-by: Andrew Lunn
Link: https://lore.kernel.org/r/E1jxtRj-0003Tz-CG@rmk-PC.armlinux.org.uk
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin -
[ Upstream commit 08b0ad375ca66181faee725b1b358bcae8d592ee ]
If CONFIG_DEBUG_SHIRQ was enabled, r8a77951-salvator-xs could boot
correctly. If we appended "earlycon keep_bootcon" to the kernel
command like, we could get kernel log like below.SError Interrupt on CPU0, code 0xbf000002 -- SError
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.8.0-rc3-salvator-x-00505-g6c843129e6faaf01 #785
Hardware name: Renesas Salvator-X 2nd version board based on r8a77951 (DT)
pstate: 60400085 (nZCv daIf +PAN -UAO BTYPE=--)
pc : rcar_gen3_phy_usb2_irq+0x14/0x54
lr : free_irq+0xf4/0x27cThis means free_irq() calls the interrupt handler while PM runtime
is not getting if DEBUG_SHIRQ is enabled and rcar_gen3_phy_usb2_probe()
failed. To fix the issue, move the irq registration place to
rcar_gen3_phy_usb2_init() which is ready to handle the interrupts.Note that after the commit 549b6b55b005 ("phy: renesas: rcar-gen3-usb2:
enable/disable independent irqs") which is merged into v5.2, since this
driver creates multiple phy instances, needs to check whether one of
phy instances is initialized. However, if we backport this patch to v5.1
or less, we don't need to check it because such kernel have single
phy instance.Reported-by: Wolfram Sang
Reported-by: Geert Uytterhoeven
Fixes: 9f391c574efc ("phy: rcar-gen3-usb2: add runtime ID/VBUS pin detection")
Signed-off-by: Yoshihiro Shimoda
Link: https://lore.kernel.org/r/1594986297-12434-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin -
[ Upstream commit dcbabfeb17c3c2fdb6bc92a3031ecd37df1834a8 ]
PHY calibration is needed only for USB2.0 (UTMI) PHY, so skip calling
calibration code when phy_calibrate() is called for USB3.0 (PIPE3) PHY.Fixes: d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800")
Signed-off-by: Marek Szyprowski
Acked-by: Krzysztof Kozlowski
Link: https://lore.kernel.org/r/20200708133800.3336-1-m.szyprowski@samsung.com
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin
18 Aug, 2020
1 commit
-
GENMASK(h, l) is creating a contiguous bitmask starting at bit
position @l and ending at position @h.Reviewed-by: Peter Chen
Reviewed-by: Peng Fan
Signed-off-by: Li Jun
(cherry picked from commit 56075f3d8b4da4ddf90f699832bbc3a6c14e381f)
22 Jul, 2020
1 commit
-
[ Upstream commit 38b1927e5bf9bcad4a2e33189ef1c5569f9599ba ]
Currently pointer phy0 is being dereferenced via the assignment of
phy on the call to phy_get_drvdata before phy0 is null checked, this
can lead to a null pointer dereference. Fix this by performing the
null check on phy0 before the call to phy_get_drvdata. Also replace
the phy0 == NULL check with the more usual !phy0 idiom.Addresses-Coverity: ("Dereference before null check")
Fixes: e6f32efb1b12 ("phy: sun4i-usb: Make sure to disable PHY0 passby for peripheral mode")
Signed-off-by: Colin Ian King
Link: https://lore.kernel.org/r/20200625124428.83564-1-colin.king@canonical.com
Signed-off-by: Vinod Koul
Signed-off-by: Sasha Levin
17 Jul, 2020
1 commit
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Correct the clock mode of PCIe PHY.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
15 Jul, 2020
1 commit
-
support pixel clock rate 135.58/137.52/162/154MHz.
Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
24 Jun, 2020
2 commits
-
[ Upstream commit 6f0577d1411337a0d97d545abe4a784e9e611516 ]
During different reboot cycles, USB PHY PLL may not always lock
during initialization and therefore can cause USB to be not usable.Hence do not use internal FSM programming sequence for the USB
PHY initialization.Fixes: 4dcddbb38b64 ("phy: sr-usb: Add Stingray USB PHY driver")
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
Link: https://lore.kernel.org/r/20200513173947.10919-1-rayagonda.kokatanur@broadcom.com
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin -
Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
- sequence should be the following one.
phy configuration--> CMN_RSTN--> wait for pll lock
- add the calibrate callback to fit the correct init sequence of phySigned-off-by: Richard Zhu
Reviewed-by: Fugang Duan
19 Jun, 2020
1 commit
-
* tag 'v5.4.47': (2193 commits)
Linux 5.4.47
KVM: arm64: Save the host's PtrAuth keys in non-preemptible context
KVM: arm64: Synchronize sysreg state on injecting an AArch32 exception
...Conflicts:
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/common.h
arch/arm/mach-imx/suspend-imx6.S
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
arch/powerpc/include/asm/cacheflush.h
drivers/cpufreq/imx6q-cpufreq.c
drivers/dma/imx-sdma.c
drivers/edac/synopsys_edac.c
drivers/firmware/imx/imx-scu.c
drivers/net/ethernet/freescale/fec.h
drivers/net/ethernet/freescale/fec_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
drivers/net/phy/phy_device.c
drivers/perf/fsl_imx8_ddr_perf.c
drivers/usb/cdns3/gadget.c
drivers/usb/dwc3/gadget.c
include/uapi/linux/dma-buf.hSigned-off-by: Jason Liu
19 May, 2020
1 commit
-
Sync code change with LF branch.
Remove head file and empty functions.
Correct some comments and types of return value.Signed-off-by: Sandor Yu
Reviewed-by: Liu Ying
14 May, 2020
1 commit
-
- Don't limit to only PCIe GEN1 when do the compliance tests.
- Configure the TX drive level of iMX865 PHY, adjust the peak output
voltage to pass the PCIe GEN1 compliance tests.Signed-off-by: Richard Zhu
Reviewed-by: Frank Li
09 May, 2020
4 commits
-
As we use internal MPLL clocks instead of alternate clocks, so
disable alternate clock to save the PHY power when SS PHY at P3.Reviewed-by: Peter Chen
Signed-off-by: Li Jun -
This patch adds runtime PM support for the Mixel LVDS combo PHY driver.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
This patch adds runtime PM support for the Mixel LVDS PHY driver.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu -
This patch adds runtime PM support for the i.MX8mp LVDS PHY driver.
Signed-off-by: Liu Ying
Reviewed-by: Sandor Yu
23 Apr, 2020
1 commit
-
[ Upstream commit 9376fa634afc207a3ce99e0957e04948c34d6510 ]
Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is
equivalent to Pro4.Signed-off-by: Kunihiko Hayashi
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
31 Mar, 2020
2 commits
-
According to IC engineer suggestion, set ssc_range as -4003 ppm
will have more tolerence for EMI, and suitable for more boards.
Besides, one customer board needs to set this value to pass TX
SSC test.Signed-off-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit a48a65a40113b9b5d40114d02a5877d089f523a9) -
This is to resolve the problem of wakeup system by USB3 device
insertion if hsiomix on, in that case, the USB3 device detects
rx term on so doesn't donwgrade to USB2, so DP/DM wakeup can't
happen, with this override bit we can force the rx term off when
enters system suspend, and disable the override after system resume.Reviewed-by: Peter Chen
Signed-off-by: Li Jun
25 Mar, 2020
2 commits
-
[ Upstream commit 58aa7729310db04ffcc022c98002dd8fcb486c58 ]
The "gmii" PHY interface mode is supported on TI AM335x/437x/5xx SoCs, so
don't fail if it's selected.Signed-off-by: Grygorii Strashko
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin -
[ Upstream commit eefed634eb61e4094b9fb8183cb8d43b26838517 ]
- under PHY_INTERFACE_MODE_MII the 'mode' func parameter is assigned
instead of 'gmii_sel_mode' and it's working only because the default value
'gmii_sel_mode' is set to 0.- console outputs use 'rgmii_id' and 'mode' values to print PHY mode
instead of using 'submode' value which is representing PHY interface mode
now.This patch fixes above two cases.
Signed-off-by: Grygorii Strashko
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
18 Mar, 2020
1 commit
-
The phy registers are accessible after APB clock is enabled,
otherwise, the system may hang. We see the system hang issue
at the driver resume stage due to the disabled APB clock.
This patch fixes this issue by enabling/disabling the clock
when necessary.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying
12 Mar, 2020
2 commits
-
commit 46b7edf1c7b7c91004c4db2c355cbd033f2385f9 upstream.
I've noticed that when writing data to the modem the writes can time out
at some point eventually. Looks like kicking the modem idle GPIO every
600 ms instead of once a second fixes the issue. Note that this rate is
different from our runtime PM autosuspend rate MDM6600_MODEM_IDLE_DELAY_MS
that we still want to keep at 1 second, so let's add a separate define for
PHY_MDM6600_IDLE_KICK_MS.Fixes: f7f50b2a7b05 ("phy: mapphone-mdm6600: Add runtime PM support for n_gsm on USB suspend")
Cc: Marcel Partap
Cc: Merlijn Wajer
Cc: Michael Scott
Cc: NeKit
Cc: Pavel Machek
Cc: Sebastian Reichel
Signed-off-by: Tony Lindgren
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Greg Kroah-Hartman -
commit be4e3c737eebd75815633f4b8fd766defaf0f1fc upstream.
We have an interrupt handler for the wake-up GPIO pin, but we're missing
the code to wake-up the system. This can cause timeouts receiving data
for the UART that shares the wake-up GPIO pin with the USB PHY.All we need to do is just wake the system and kick the autosuspend
timeout to fix the issue.Fixes: 5d1ebbda0318 ("phy: mapphone-mdm6600: Add USB PHY driver for MDM6600 on Droid 4")
Cc: Marcel Partap
Cc: Merlijn Wajer
Cc: Michael Scott
Cc: NeKit
Cc: Pavel Machek
Cc: Sebastian Reichel
Signed-off-by: Tony Lindgren
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Greg Kroah-Hartman
11 Mar, 2020
1 commit
-
Move clock rate config table to phy-fsl-samsung-hdmi.h.
Support mode pixel rates.Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
08 Mar, 2020
1 commit
-
Merge Linux stable release v5.4.24 into imx_5.4.y
* tag 'v5.4.24': (3306 commits)
Linux 5.4.24
blktrace: Protect q->blk_trace with RCU
kvm: nVMX: VMWRITE checks unsupported field before read-only field
...Signed-off-by: Jason Liu
Conflicts:
arch/arm/boot/dts/imx6sll-evk.dts
arch/arm/boot/dts/imx7ulp.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
drivers/clk/imx/clk-composite-8m.c
drivers/gpio/gpio-mxc.c
drivers/irqchip/Kconfig
drivers/mmc/host/sdhci-of-esdhc.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
drivers/net/can/flexcan.c
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
drivers/net/ethernet/mscc/ocelot.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
drivers/net/phy/realtek.c
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
drivers/perf/fsl_imx8_ddr_perf.c
drivers/tee/optee/shm_pool.c
drivers/usb/cdns3/gadget.c
kernel/sched/cpufreq.c
net/core/xdp.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.c
sound/soc/sof/core.c
sound/soc/sof/imx/Kconfig
sound/soc/sof/loader.c
13 Feb, 2020
2 commits
-
The i.MX8mp LVDS PHY IP contains two PHYs, each of which
supports a four data lane LVDS channel.
This patch adds i.MX8mp LVDS PHY driver support.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
To enable iMX8MP PCIe support, add the standalone PHY driver.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
11 Feb, 2020
1 commit
-
commit a89806c998ee123bb9c0f18526e55afd12c0c0ab upstream.
Clang warns:
../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:83:4: warning:
misleading indentation; statement is not part of the previous 'if'
[-Wmisleading-indentation]
usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
^
../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:80:3: note: previous
statement is here
if (readl_relaxed(addr) & mask)
^
1 warning generated.This warning occurs because there is a space after the tab on this line.
Remove it so that the indentation is consistent with the Linux kernel
coding style and clang no longer warns.Fixes: 1de990d8a169 ("phy: qcom: Add driver for QCOM APQ8064 SATA PHY")
Link: https://github.com/ClangBuiltLinux/linux/issues/816
Signed-off-by: Nathan Chancellor
Reviewed-by: Bjorn Andersson
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Greg Kroah-Hartman
01 Feb, 2020
2 commits
-
[ Upstream commit 63078b6ba09e842f09df052c5728857389fddcd2 ]
The micro-USB connector on Motorola Mapphone devices can be muxed between
the SoC and the mdm6600 modem. But even when used for the SoC, configuring
the PHY with ID pin grounded will wake up the modem from idle state. Looks
like the issue is probably caused by line glitches.We can prevent the glitches by using a previously unknown mode of the
GPIO mux to prevent the USB lines from being connected to the moden while
configuring the USB PHY, and enable the USB lines after configuring the
PHY.Note that this only prevents waking up mdm6600 as regular USB A-host mode,
and does not help when connected to a lapdock. The lapdock specific issue
still needs to be debugged separately.Cc: Merlijn Wajer
Cc: Pavel Machek
Cc: Sebastian Reichel
Acked-by: Pavel Machek
Signed-off-by: Tony Lindgren
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin -
[ Upstream commit cd217ee6867d285ceecd610fa1006975d5c683fa ]
It's typical for the QHP PHY to take slightly above 1ms to initialize,
so increase the timeout of the PHY ready check to 10ms - as already done
in the downstream PCIe driver.Signed-off-by: Bjorn Andersson
Tested-by: Evan Green
Tested-by: Vinod Koul
Signed-off-by: Vinod Koul
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
26 Jan, 2020
1 commit
-
[ Upstream commit 4f510aa10468954b1da4e94689c38ac6ea8d3627 ]
Commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework")
changed what rate clk_round_rate() is called with, an additional 999 Hz
added to the requsted mode clock. This has caused a regression on RK3328
and presumably also on RK3228 because the inno-hdmi-phy clock requires an
exact match of the requested rate in the pre pll config table.When an exact match is not found the parent clock rate (24MHz) is returned
to the clk_round_rate() caller. This cause wrong pixel clock to be used and
result in no-signal when configuring a mode on RK3328.Fix this by rounding the rate down to closest 1000 Hz in round_rate func,
this allows an exact match to be found in pre pll config table.Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework")
Signed-off-by: Jonas Karlman
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sasha Levin
