21 Aug, 2020
1 commit
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[ Upstream commit 5f77d6ca5ca74e4b4a5e2e010f7ff50c45dea326 ]
Set proper masks to avoid invalid input spillover to reserved bits.
Signed-off-by: Liu Yi L
Signed-off-by: Jacob Pan
Signed-off-by: Lu Baolu
Reviewed-by: Eric Auger
Link: https://lore.kernel.org/r/20200724014925.15523-2-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel
Signed-off-by: Sasha Levin
01 Apr, 2020
1 commit
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[ Upstream commit ba3b01d7a6f4ab9f8a0557044c9a7678f64ae070 ]
Commit 6825d3ea6cde ("iommu/vt-d: Add debugfs support to show register
contents") dumps the register contents for all IOMMU devices.Currently, a 64 bit read(dmar_readq) is done for all the IOMMU registers,
even though some of the registers are 32 bits, which is incorrect.Use the correct read function variant (dmar_readl/dmar_readq) while
reading the contents of 32/64 bit registers respectively.Signed-off-by: Megha Dey
Link: https://lore.kernel.org/r/1583784587-26126-2-git-send-email-megha.dey@linux.intel.com
Acked-by: Lu Baolu
Signed-off-by: Joerg Roedel
Signed-off-by: Sasha Levin
11 Nov, 2019
1 commit
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For both PASID-based-Device-TLB Invalidate Descriptor and
Device-TLB Invalidate Descriptor, the Physical Function Source-ID
value is split according to this layout:PFSID[3:0] is set at offset 12 and PFSID[15:4] is put at offset 52.
Fix the part laid out at offset 52.Fixes: 0f725561e1684 ("iommu/vt-d: Add definitions for PFSID")
Signed-off-by: Eric Auger
Acked-by: Jacob Pan
Cc: stable@vger.kernel.org # v4.19+
Acked-by: Lu Baolu
Signed-off-by: Joerg Roedel
11 Sep, 2019
2 commits
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… 'arm/renesas', 'x86/amd', 'x86/vt-d' and 'core' into next
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Intel VT-d specification revision 3 added support for Scalable Mode
Translation for DMA remapping. Add the Scalable Mode fault reasons to
show detailed fault reasons when the translation fault happens.Link: https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf
Reviewed-by: Sohil Mehta
Signed-off-by: Kyung Min Park
Signed-off-by: Joerg Roedel
03 Sep, 2019
1 commit
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Global pages support is removed from VT-d spec 3.0. Since global pages G
flag only affects first-level paging structures and because DMA request
with PASID are only supported by VT-d spec. 3.0 and onward, we can
safely remove global pages support.For kernel shared virtual address IOTLB invalidation, PASID
granularity and page selective within PASID will be used. There is
no global granularity supported. Without this fix, IOTLB invalidation
will cause invalid descriptor error in the queued invalidation (QI)
interface.Fixes: 1c4f88b7f1f9 ("iommu/vt-d: Shared virtual address in scalable mode")
Reported-by: Sanjay K Kumar
Signed-off-by: Jacob Pan
Signed-off-by: Joerg Roedel
04 Jul, 2019
1 commit
05 Jun, 2019
1 commit
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Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not write to the free
software foundation inc 59 temple place suite 330 boston ma 02111
1307 usaextracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 33 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Allison Randal
Reviewed-by: Kate Stewart
Reviewed-by: Alexios Zavras
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190530000435.254582722@linutronix.de
Signed-off-by: Greg Kroah-Hartman
28 May, 2019
1 commit
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Previously, get_valid_domain_for_dev() is used to retrieve the
DMA domain which has been attached to the device or allocate one
if no domain has been attached yet. As we have delegated the DMA
domain management to upper layer, this function is used purely to
allocate a private DMA domain if the default domain doesn't work
for ths device. Cleanup the code for readability.Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel
27 May, 2019
1 commit
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A scalable mode DMAR table walk would involve looking at bits in each stage
of walk, like,
1. Is PASID enabled in the context entry?
2. What's the size of PASID directory?
3. Is the PASID directory entry present?
4. Is the PASID table entry present?
5. Number of PASID table entries?Hence, add these macros that will later be used during this walk.
Apart from adding new macros, move existing macros (like
pasid_pde_is_present(), get_pasid_table_from_pde() and pasid_supported())
to appropriate header files so that they could be reused.Cc: Joerg Roedel
Cc: Ashok Raj
Cc: Lu Baolu
Cc: Sohil Mehta
Cc: David Woodhouse
Cc: Jacob Pan
Cc: Andy Shevchenko
Reviewed-by: Lu Baolu
Reviewed-by: Andy Shevchenko
Signed-off-by: Sai Praneeth Prakhya
Signed-off-by: Joerg Roedel
11 Apr, 2019
3 commits
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When multiple domains per device has been enabled by the
device driver, the device will tag the default PASID for
the domain to all DMA traffics out of the subset of this
device; and the IOMMU should translate the DMA requests
in PASID granularity.This adds the intel_iommu_aux_attach/detach_device() ops
to support managing PASID granular translation structures
when the device driver has enabled multiple domains per
device.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel -
This adds the iommu ops entries for aux-domain per-device
feature query and enable/disable.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel -
This moves intel_iommu_enable_pasid() out of the scope of
CONFIG_INTEL_IOMMU_SVM with more and more features requiring
pasid function.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel
11 Jan, 2019
1 commit
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VT-d Rev3.0 has made a few changes to the page request interface,
1. widened PRQ descriptor from 128 bits to 256 bits;
2. removed streaming response type;
3. introduced private data that requires page response even the
request is not last request in group (LPIG).This is a supplement to commit 1c4f88b7f1f92 ("iommu/vt-d: Shared
virtual address in scalable mode") and makes the svm code compliant
with VT-d Rev3.0.Cc: Ashok Raj
Cc: Liu Yi L
Cc: Kevin Tian
Signed-off-by: Jacob Pan
Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode")
Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel
11 Dec, 2018
8 commits
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Deferred invalidation is an ECS specific feature. It will not be
supported when IOMMU works in scalable mode. As we deprecated the
ECS support, remove deferred invalidation and cleanup the code.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Cc: Sanjay Kumar
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
Signed-off-by: Joerg Roedel -
This patch enables the current SVA (Shared Virtual Address)
implementation to work in the scalable mode.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
Signed-off-by: Joerg Roedel -
This adds an interface to setup the PASID entries for first
level page table translation.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
Signed-off-by: Joerg Roedel -
This patch enables the translation for requests without PASID in
the scalable mode by setting up the root and context entries.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
Signed-off-by: Joerg Roedel -
This adds the interfaces to setup or tear down the structures
for second level page table translations. This includes types
of second level only translation and pass through.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
Signed-off-by: Joerg Roedel -
Intel vt-d spec rev3.0 requires software to use 256-bit
descriptors in invalidation queue. As the spec reads in
section 6.5.2:Remapping hardware supporting Scalable Mode Translations
(ECAP_REG.SMTS=1) allow software to additionally program
the width of the descriptors (128-bits or 256-bits) that
will be written into the Queue. Software should setup the
Invalidation Queue for 256-bit descriptors before progra-
mming remapping hardware for scalable-mode translation as
128-bit descriptors are treated as invalid descriptors
(see Table 21 in Section 6.5.2.10) in scalable-mode.This patch adds 256-bit invalidation descriptor support
if the hardware presents scalable mode capability.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel -
So that they could also be used in other source files.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Cc: Sanjay Kumar
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
Reviewed-by: Kevin Tian
Signed-off-by: Joerg Roedel -
The Intel vt-d spec rev3.0 introduces a new translation
mode called scalable mode, which enables PASID-granular
translations for first level, second level, nested and
pass-through modes. At the same time, the previous
Extended Context (ECS) mode is deprecated (no production
ever implements ECS).This patch adds enumeration for Scalable Mode and removes
the deprecated ECS enumeration. It provides a boot time
option to disable scalable mode even hardware claims to
support it.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Signed-off-by: Sanjay Kumar
Signed-off-by: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
Reviewed-by: Kevin Tian
Signed-off-by: Joerg Roedel
12 Nov, 2018
1 commit
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Commit e61d98d8dad00 ("x64, x2apic/intr-remap: Intel vt-d, IOMMU
code reorganization") moved dma_remapping.h from drivers/pci/ to
current place. It is entirely VT-d specific, but uses a generic
name. This merges dma_remapping.h with include/linux/intel-iommu.h
and removes dma_remapping.h as the result.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Sohil Mehta
Suggested-by: Christoph Hellwig
Signed-off-by: Lu Baolu
Reviewed-by: Christoph Hellwig
Reviewed-by: Liu, Yi L
Signed-off-by: Joerg Roedel
25 Sep, 2018
3 commits
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Add a new config option CONFIG_INTEL_IOMMU_DEBUGFS and do the base
enabling for Intel IOMMU debugfs.Cc: Lu Baolu
Cc: Fenghua Yu
Cc: Ashok Raj
Cc: Jacob Pan
Co-Developed-by: Gayatri Kammela
Signed-off-by: Gayatri Kammela
Reviewed-by: Andy Shevchenko
Reviewed-by: Lu Baolu
Signed-off-by: Sohil Mehta
Signed-off-by: Joerg Roedel -
Add new register definitions added in the VT-d 3.0 specification. Also
include registers that were missing previously.Cc: Lu Baolu
Cc: Fenghua Yu
Cc: Jacob Pan
Cc: Ashok Raj
Cc: Gayatri Kammela
Signed-off-by: Sohil Mehta
Signed-off-by: Joerg Roedel -
To reuse the static functions and the struct declarations, move them to
corresponding header files and export the needed functions.Cc: Lu Baolu
Cc: Fenghua Yu
Cc: Jacob Pan
Cc: Ashok Raj
Reviewed-by: Andy Shevchenko
Signed-off-by: Gayatri Kammela
Signed-off-by: Sohil Mehta
Signed-off-by: Joerg Roedel
08 Aug, 2018
1 commit
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… 'x86/amd', 'x86/vt-d' and 'core' into next
20 Jul, 2018
7 commits
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The obsolete per iommu pasid tables are no longer used. Hence,
clean up them.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Liu Yi L
Signed-off-by: Joerg Roedel -
This patch adds the interfaces for per PCI device pasid
table management. Currently we allocate one pasid table
for all PCI devices under the scope of an IOMMU. It's
insecure in some cases where multiple devices under one
single IOMMU unit support PASID features. With per PCI
device pasid table, we can achieve finer protection and
isolation granularity.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Suggested-by: Ashok Raj
Signed-off-by: Lu Baolu
Reviewed-by: Liu Yi L
Signed-off-by: Joerg Roedel -
This adds a helper named for_each_device_domain() to iterate
over the elements in device_domain_list and invoke a callback
against each element. This allows to search the device_domain
list in other source files.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Liu Yi L
Signed-off-by: Joerg Roedel -
This allows the per device iommu data and some helpers to be
used in other files.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Liu Yi L
Signed-off-by: Joerg Roedel -
This patch applies the global pasid name space in the shared
virtual address (SVA) implementation.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Kevin Tian
Reviewed-by: Liu Yi L
Reviewed-by: Peter Xu
Signed-off-by: Joerg Roedel -
idr_for_each_entry() is used to iteratte over idr elements
of a given type. It isn't suitable for the globle pasid idr
since the pasid idr consumer could specify different types
of pointers to bind with a pasid.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Kevin Tian
Reviewed-by: Liu Yi L
Reviewed-by: Peter Xu
Signed-off-by: Joerg Roedel -
This reverts commit ab96746aaa344fb720a198245a837e266fad3b62.
The commit ab96746aaa34 ("iommu/vt-d: Clean up pasid quirk for
pre-production devices") triggers ECS mode on some platforms
which have broken ECS support. As the result, graphic device
will be inoperable on boot.Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107017
Cc: Ashok Raj
Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel
06 Jul, 2018
2 commits
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PFSID should be used in the invalidation descriptor for flushing
device IOTLBs on SRIOV VFs.Signed-off-by: Jacob Pan
Cc: stable@vger.kernel.org
Cc: "Ashok Raj"
Cc: "Lu Baolu"
Signed-off-by: Joerg Roedel -
When SRIOV VF device IOTLB is invalidated, we need to provide
the PF source ID such that IOMMU hardware can gauge the depth
of invalidation queue which is shared among VFs. This is needed
when device invalidation throttle (DIT) capability is supported.This patch adds bit definitions for checking and tracking PFSID.
Signed-off-by: Jacob Pan
Cc: stable@vger.kernel.org
Cc: "Ashok Raj"
Cc: "Lu Baolu"
Signed-off-by: Joerg Roedel
15 May, 2018
1 commit
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The pasid28 quirk is needed only for some pre-production devices.
Remove it to make the code concise.Signed-off-by: Ashok Raj
Signed-off-by: Lu Baolu
Signed-off-by: Joerg Roedel
14 Feb, 2018
1 commit
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So one could decode them without opening the specification.
Signed-off-by: Dmitry Safonov
Signed-off-by: Joerg Roedel
17 Jan, 2018
2 commits
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Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.Signed-off-by: Sohil Mehta
Signed-off-by: Joerg Roedel -
Add a check to verify IOMMU 1GB page support. If the CPU supports 1GB
pages but the IOMMU does not support it then disable SVM by not
allocating PASID tables.Signed-off-by: Sohil Mehta
Signed-off-by: Joerg Roedel