09 Jun, 2017
4 commits
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In defalut, most of i.MX boards share one MII bus in boards design to reduce
pins utilize, but others each MAC use their exclusive MII bus. To solve the
problem, user can select to define the mii-exclusive property in board dts file.The patch also update binding doc.
Signed-off-by: Fugang Duan
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Register Athreos PHY AR8031 fixup.
Signed-off-by: Fugang Duan
(cherry picked and merged from commit:676bf1d92b3e6babdab623694fd83d54f881fc2f) -
Add dts property "phy-reset-gpios" PROBE_DEFER check, and use
gpio_set_value_cansleep() due to the FEC PHY reset gpio may be on
an I2C expander.Signed-off-by: Fugang Duan
(cherry picked from commit: 3b63e39f460d239c19a5afaf281d9a512b958cf7) -
Add FEC support for NXP i.MX8x chips.
Signed-off-by: Fugang Duan
08 Jun, 2017
36 commits
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- move imx_rpmsg from arch/arm/ to drivers/rpmsg.
- use the new MU generic APIs in the rpmsg implementation.
- Validated the pingpong test on both imx6sx and imx7d sdb boards.Signed-off-by: Richard Zhu
-
- add the MU version1.0 (introduced by 7ulp)
support.
- add the MU_SetFn and MU_ReadStatus APIs.
- fix one mispell bug when enable the RX INTs.
Otherwise, the RX INTs wouldn't be configured
correctly.Signed-off-by: Richard Zhu
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Fix the logic error when reading dummy cycle for qspi ddr quad mode
Signed-off-by: Han Xu
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Signed-off-by: Octavian Purdila
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The ci_handle_id_switch is called at two places, at very rare situations,
it may be running at the same time. Eg, when the system is back from
the resume, the id event is occurred from extcon driver, as well as
power_lost work item is called due to the controller is poweroff at
the suspend.Signed-off-by: Peter Chen
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Gadget state is set to be suspended when bus suspened, but not updated
after resume, this patch saves the gadget state before suspend and
restores it after resume.Acked-by: Peter Chen
Signed-off-by: Li Jun -
Missing NULL checks in CAAM sm_store and sm_test cause kernel
crashes if caam init fails.Signed-off-by: Radu Solea
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This fixes crashing on boot on imx7d if imx_src_is_m4_enabled(). This
check was lost when porting 24ee04ce76d6a8d8229c642eb5d7a15ea57570c6.Signed-off-by: Leonard Crestez
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The LCDIF driver fails at boot time because it cannot read display timings
from device tree. This is a fake error because the LCDIF DT node contains a
display device property which leads to the display driver that also provides
the timings.This fake error case has been introduced by
commit 5443a75ed038 ("MLK-14283: dts: fix DE polarity for lcdif") and
commit 56412d6a83d8 ("MLK-13996: lcdif: Use DE polarity specified in DTS")
which fixed DE polarity panel differences for different boards.This patch adds support for choosing a particular video mode from the ones
provided by the display driver, thus also fixing the DE polarity issue
initially fixed by the above mentioned 2 patches.Signed-off-by: Cristina Ciocan
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This reverts commit 56412d6a83d8 ("MLK-13996: lcdif: Use DE polarity
specified in DTS").We need to take the display timings from "disp-dev" if such node exists.
Revert this patch because it tries to find the display-timings in the
display controller node, even though it has been found in the display
device node.Signed-off-by: Cristina Ciocan
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Fix IPU2 DI(Display Interface) clocks for iMX6QP SABRESD. The upstream
version uses ldb_di0_podf and ldb_di1_podf as clock parents for ipu_di,
which fails to work on iMX6QP SABRESD. This patch fixes clock tree by:
- setting ipu_di selectors to ldb_di_div_sel in imx6q clock driver
- matching "ldb_di0", "ldb_di1" clock names with
IMX6QDL_CLK_LDB_DI0_DIV_SEL, IMX6QDL_CLK_LDB_DI1_DIV_SEL; otherwise,
ldb_di0_div_sel and ldb_di1_div_sel will not be recognized as LDB clk parents
and will not drive the Display Interface.Signed-off-by: Cristina Ciocan
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1. unique need to be set to get proper busid.
Vivante driver is very simple and does not use drm_dev_alloc
which in turn calls drm_dev_set_unique.
Use set_busid to set the unique.https://patchwork.kernel.org/patch/9182749/
2. driver_features = DRIVER_LEGACY added to do mmap of SHM.
https://patchwork.kernel.org/patch/8694561/fix the problem that X11 cannot work with 4.9 kernel upgrade
Signed-off-by: Prabhu Sundararaj
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mtd->priv is no longer pointing to the struct nand_chip it is attached
to. Replace those accesses by mtd_to_nand() calls.Signed-off-by: Octavian Purdila
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Remove the redundant codes in pcie-designware driver.
Because that the class configration had been
contained in 4.9 kernel.Signed-off-by: Richard Zhu
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- Do not return error when the GEN2 link negatiation
is failed. Because that the limitation maybe caused
by the remote GEN1 EP device.
- Move the power saving codes to the proper place
after the link is down.
Otherwise, system would hang when link is down.Signed-off-by: Richard Zhu
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Upstream rejected this patch because it is wrong: Attaching clk and
regulator resources to the cpu device results in them never actually
getting freed.This is relevant now that we rely on supporting EPROBE_DEFER because we
must handle correctly returning from a partial probe.In particular this patch fixes imx6qp-sabresd not setting the PU
regulator to bypass mode because the cpufreq driver fetched the
regulator before gpc and leaked it.This is not a straight revert because other clks and regulators were
added, we add code to free them too.Signed-off-by: Leonard Crestez
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When setting passive temperature trip point, it is not
allowed to set a higher value than the default.Currently the driver compares the new temperature to set
with a constant (0). This comparison wil always be true
(temp to set higher than 0) and the driver will return
-EINVAL. This is a leftover from rebasing the commit fc4fcd689419
("MLK-11705 thermal: imx: make the critical trip temp changable for test").Fix the comparison by using the actual default passive
temperature value instead of the wrong constant.Signed-off-by: Irina Tirdea
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The Linux kernel regulator core implementation does not accept negative
voltage values; all negative values are treated as errors.The problem with the EPDC is that the panel uses a negative voltage
regulator which fails to be enabled by the regulator core. This issue has
slipped up until the 4.9 rebase because the voltage range [min, max] was
checked against only when min = max. This has been fixed in 4.9, resulting
in errors in the VCOM regulator driver.The fix is to use the negative values when communicating with the hardware,
but send only positive values to the regulator core.This patch sends the absolute value to the regulator core and transforms
the received value (from the regulator core) to negative one before sending
it to hardware.Fix device tree to deal with negative voltage regulator values by setting
min_value = -real_max_value and vice versa. Boards affected:
- imx6dl-sabresd
- imx6ull-14x14-ddr3-arm2
- imx7d-12x12-lpddr3-arm2
- imx7d-sdb
- imx6sll-evk
- imx6sl-evk
- imx6sll-lpddr3-arm2Signed-off-by: Cristina Ciocan
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Currently, the LCDIF driver (mxsfb.c) is overriding the DE polarity
specified in DTS with the one specified in fb_videomode (sync member) by
the panel driver.
Initially, the panel driver found in
drivers/video/fbdev/mxc/mxcfb_hx8363_wvga.c specified the sync in
fb_videomode as FB_SYNC_OE_LOW_ACT.But this patch, changed it to 0x0:
commit 4deb430fd05a ("MLK-13607-8 video: mipi-panel: hx8363: change DE
polarity to active high")
Author: Fancy Fang
Date: Wed Dec 14 16:21:51 2016 +0800The NorthWest Logic MIPI DSI only support active low data enable
signal on imx7ulp-evk board.The problem is that, the hx8363 panel was working with active low on
imx7d-sdb, but with active high on imx7ulp-evk. The above patch broke
hx8363 panel on imx7d-sdb board.So, instead of using a hard-coded polarity in panel driver, better use
the one defined in device-tree.Signed-off-by: Robert Chiras
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The mxsfb framebuffer driver uses three clock definitions, but only two
are defined in DTS for imx7s (also used by imx7d); because of this,
driver fails in probe. Since iMX7D uses only one clock, add the third clock
and make two of them dummy.
Also, add additional error messages for better identification of a
failing probe.Signed-off-by: Robert Chiras
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It is wrong to pass 'int' to IS_ERR_VALUE(), Linus's commit
aa00edc1 point out this abuse.This patch use operator instead.
Signed-off-by: Haibo Chen
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Multi drivers(mmc, cpufreq..) may access pf1550 regulator rpmsg driver at
the same time, so we have to add mutex for this multi-entry case. Otherwise
the below kernel warning maybe triggered:------------[ cut here ]------------
WARNING: CPU: 0 PID: 19 at kernel/power/qos.c:453 pf1550_send_message+0x4c/0xf8()
pm_qos_add_request() called for already added request
Modules linked in:
CPU: 0 PID: 19 Comm: kworker/0:1 Not tainted 4.1.33-02293-g80b8c19 #636
Hardware name: Freescale i.MX7ULP (Device Tree)
Workqueue: events od_dbs_timer
[] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[] (show_stack) from [] (dump_stack+0x88/0x9c)
[] (dump_stack) from [] (warn_slowpath_common+0x80/0xb0)
[] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
[] (warn_slowpath_fmt) from [] (pf1550_send_message+0x4c/0xf8)
[] (pf1550_send_message) from [] (pf1550_get_voltage+0x48/0x5c)
[] (pf1550_get_voltage) from [] (_regulator_get_voltage+0x68/0xb4)
[] (_regulator_get_voltage) from [] (_regulator_do_set_voltage+0x5c/0x3e4)
[] (_regulator_do_set_voltage) from [] (regulator_set_voltage+0xb0/0x14c)
[] (regulator_set_voltage) from [] (imx7ulp_set_target+0x178/0x238)
[] (imx7ulp_set_target) from [] (__cpufreq_driver_target+0x164/0x294)
[] (__cpufreq_driver_target) from [] (dbs_check_cpu+0x1a0/0x1e0)
[] (dbs_check_cpu) from [] (od_dbs_timer+0x80/0x138)
[] (od_dbs_timer) from [] (process_one_work+0x118/0x3e4)
[] (process_one_work) from [] (worker_thread+0x4c/0x4f4)
[] (worker_thread) from [] (kthread+0xdc/0xf4)
[] (kthread) from [] (ret_from_fork+0x14/0x2c)
---[ end trace f8281ecde7a0b4ce ]---
------------[ cut here ]------------Signed-off-by: Robin Gong
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Put the three dsi domains into reset state when dsi is disabled
to avoid dsi being an unstable state before next time enabled.Signed-off-by: Fancy Fang
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Put the three dsi domains into reset state before dsi is
shutdown to avoid dsi being a unstable state.Signed-off-by: Fancy Fang
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The overlay framebuffer fb1 access maybe accessed when fb0
is in the blank state in which all the lcd clocks have been
disabled.Signed-off-by: Fancy Fang
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In the mipi_dsi_shutdown() function, it accesses some dsi registers.
But in some cases, the esc_clk may be disabled at this moment. So
first enable this clock then do other shutdown works. Otherwise,
it may cause kernel panic dump as belows when rebooting system:Unhandled fault: imprecise external abort (0x1c06) at 0x0033802c
pgd = b0a24000
[0033802c] *pgd=908f1831, *pte=6320775f, *ppte=63207c7f
Internal error: : 1c06 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 1059 Comm: reboot Not tainted 4.1.33-02248-g22f8d64-dirty #513
Hardware name: Freescale i.MX7ULP (Device Tree)
task: b0f56600 ti: b08e8000 task.ti: b08e8000
PC is at mipi_dsi_pkt_write+0x38/0x1b0
LR is at mipi_dsi_wr_tx_header.constprop.2+0x6c/0x94
pc : [] lr : [] psr: 60070013
sp : b08e9c00 ip : 00000001 fp : 00000000
r10: 00000000 r9 : b024a810 r8 : b00c5044
r7 : 80cac4d8 r6 : 80bd2504 r5 : b024a810 r4 : b024a810
r3 : c0920000 r2 : 00000000 r1 : 60070013 r0 : 00000023
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 90a2406a DAC: 00000015
Process reboot (pid: 1059, stack limit = 0xb08e8210)
Stack: (0xb08e9c00 to 0xb08ea000)
9c00: 00000000 80066e30 00000000 b00c5000 20070113 b024a810 b024a810 b00c5010
9c20: 80cac4d8 b00c5044 80c54020 00000000 00000000 802fdba4 00000028 00000000
9c40: bf672edc 00000001 80bdff40 8007ad7c 8004993c 8082eb30 00000000 80be0140
9c60: 80bcddc0 80832cd8 80c517f1 80bcddc0 b08e9c70 80bdfb40 b0004c60 00000000
9c80: 00000009 00000000 00000009 00000000 80c576c0 00000000 80bd20a8 8003b9d8
9ca0: 00000000 b08e9d68 b08e9ca0 80c576c0 0000000a ffffb7c1 80bd2100 80bcbbe8
9cc0: 00000000 80bcd800 b0f56600 bf672800 b0f56648 b00fab08 b00fab10 8005fc30
9ce0: 00000017 00000000 00000000 8006ff84 c080200c 00000026 80bd2838 b08e9d28
9d00: 80361f04 80c586d6 80c586d6 8035b2a8 80361f04 b02b3610 80bd2504 001c0700
9d20: 003c0700 8036212c 80bff3b0 80c58198 80bdf8a0 20070093 00000199 8082e868
9d40: 00000000 80bdf8a0 80c58198 00000000 00000199 8082eadc 80c58198 8006e8b0
9d60: 00000400 80c5f48c 00000029 80c98ac8 80c58198 80c98098 60070013 00000000
9d80: 80bdf880 00000001 00000000 80c58198 00000000 00000029 00000001 80c58198
9da0: 00000029 00000001 00000000 8006e654 00000000 8006ee2c 00000000 00000000
9dc0: 00000000 00000000 80c98ae6 00000029 00000000 00000000 00000000 60070013
9de0: 00000000 00000000 00000000 8006f214 b024a810 b00c5010 80cac4d8 b00c5044
9e00: 80c54020 00000000 00000000 8006f238 80a580f0 b08e9e34 00000000 80824414
9e20: 80a58148 b08e9e34 b024a810 802fdc6c 80a580f0 80872338 00000000 802fdc80
9e40: 60070013 b024a810 b00c1a10 802fdd10 802fdcf0 b00c5010 b00c1a10 8038e8a8
9e60: b00c501c 8038b3cc 01234567 00000000 80bdee38 00000000 fee1dead 8000f644
9e80: b08e8000 800529cc 00000000 80052c24 bf699000 00000001 00000000 800b3498
9ea0: 00000000 bfca9160 bf699000 80bd04b8 bfca9160 00000000 80c50880 800b5460
9ec0: b08e9ed4 00000000 b08e9ec8 00000000 b074ad10 00000000 00359000 b074a7e8
9ee0: b08e9f20 b074ad10 b0a56e00 00351000 b074ad10 800d3cb8 b0a56e00 00000000
9f00: b074ad10 00351000 00000001 00000001 b08e9f24 b0001680 00000001 00000001
9f20: b08e9f34 bf672e00 b086a240 bf672e00 ae13f550 ae13f5a0 00080040 00000001
9f40: b086a240 ae1533f0 00000000 b07e1d90 ae13f550 40000010 b086a240 800ed1b0
9f60: 00000020 00000000 b0f569f8 00000000 b0f569f8 00000000 80c57c28 b0f56600
9f80: 00000000 8004f358 b086a240 b08e8000 8000f644 7eec5e14 00000003 00000000
9fa0: 00000058 8000f4c0 7eec5e14 00000003 fee1dead 28121969 01234567 00000000
9fc0: 7eec5e14 00000003 00000000 00000058 00000000 00000000 00000000 00000000
9fe0: 76f3ec10 7eec5c7c 00010fc8 76f3ec30 60070010 fee1dead 00000000 00000000
[] (mipi_dsi_pkt_write) from [] (mipi_dsi_dcs_cmd.part.0+0x24/0x2c)
[] (mipi_dsi_dcs_cmd.part.0) from [] (mipi_display_enter_sleep+0x30/0xa0)
[] (mipi_display_enter_sleep) from [] (mipi_dsi_shutdown+0x20/0x9c)
[] (mipi_dsi_shutdown) from [] (platform_drv_shutdown+0x18/0x28)
[] (platform_drv_shutdown) from [] (device_shutdown+0xdc/0x1e4)
[] (device_shutdown) from [] (kernel_restart+0xc/0x50)
[] (kernel_restart) from [] (SyS_reboot+0xc8/0x1b8)
[] (SyS_reboot) from [] (ret_fast_syscall+0x0/0x3c)
Code: e34860bd e58da000 e1a0200c ebffff90 (f57ff04e)
---[ end trace 9f61c48a242457f2 ]---Signed-off-by: Fancy Fang
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In userspace, user can not distinguish fb0 and fb1, so add fb1/name property to
distinguish them.Signed-off-by: Guoniu.Zhou
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According to the i.MX7ULP RM & datasheet, when A7 is in RUN mode,
the max CPU frequency it can run at is 500MHz, if we want to increase
the A7 CPU frequency to 800MHz, we need to change the A7 from RUN mode
to HSRUN mode. And only when A7 is in RUN mode, we can enter STOP mode
and VLLS mode.Signed-off-by: Bai Ping
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Add HSRUN mode clocks on i.MX7ULP. we also add a fake clock mux ARM
to make the clock tree more easy to handle in cpufreq.Signed-off-by: Bai Ping
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Add gpt_3m clock source on i.MX6SLL.
Signed-off-by: Bai Ping
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Message can be transferred between remote
device and iMX7ULP M4.
Then the message can be transferred between A7
and M4 by rpmsg channel.
demo howto:
- insmode the imx_rpmsg_tty.ko module after
login A7/Linux.
- Receive messages. Used the following command
to dump out the msg from the virtual tty.
./unit_tests/mxc_mcc_tty_test.out /dev/ttyRPMSG 115200 R 100 1000 &
- Send: use the following command to send the
message to M4.
echo /dev/ttyRPMSGSigned-off-by: Richard Zhu
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At imx7ulp, any interrupts can wake system up from suspend at "standby"
mode, so we mask interrupt for gpio by default. The user can still
enable wakeup through /sys entry.Signed-off-by: Peter Chen
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The wakeup on USB port should be determined by user, but not enabled
by default.Signed-off-by: Peter Chen
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Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLKIMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.
Update copyright information.
Signed-off-by: Fugang Duan
Signed-off-by: Adrian Alonso -
In mxsfb driver, function overlayfb_check_var, a null pointer dereference
occurs if fourcc pixel format is one not considered explicitly.This case should not occur, since the pixel format is verified against
supported values before getting to this null dereference code, but this may
change if overlay_fmt_support() or overlayfb_check_var() changes and they
are not kept in sync.Signed-off-by: Cristina Ciocan
-
In function mxsfb_check_var an explicit null pointer dereference occurs
when input frame is 32 bpp (var->bits_per_pixel) and the output frame is
different from 8/16/18/24 (host->ld_intf_width).Even though a 32bpp output is possible under certain conditions, this is
currently not implemented, so any other output bpp value is not valid.Signed-off-by: Cristina Ciocan
