26 Jun, 2019
9 commits
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Tegra's timer has 29 bits for the counter and for the "load" register
which sets counter to a load-value. The counter's value is lower than
the actual value by 1 because it starts to decrement after one tick,
hence the maximum number of ticks that hardware can handle equals to
29 bits + 1.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
Tegra's timer uses n+1 scheme for the counter, i.e. timer will fire after
one tick if 0 is loaded. The minimum and maximum numbers of oneshot ticks
are defined by clockevents_config_and_register(min, max) invocation and
the min value is set to 1 tick. Hence "cycles" value can't ever be 0,
unless it's a bug in clocksource core.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
We're adjusting the timer's base for each per-CPU timer to point to the
actual start of the timer since device-tree defines a compound registers
range that includes all of the timers. In this case the original base
need to be restore before calling iounmap to unmap the proper address.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
Convert all 1MHz literals to a verbose constant for better readability.
Suggested-by: Daniel Lezcano
Acked-by: Jon Hunter
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
There is no need to cast void because kernel allows to do that without
a warning message from a compiler.Acked-by: Jon Hunter
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
The of_clk structure has a period field that is set up initially by
timer_of_clk_init(), that period value need to be adjusted for a case of
TIMER1-9 that are running at a fixed rate that doesn't match the clock's
rate. Note that the period value is currently used only by some of the
clocksource drivers internally and hence this is just a minor cleanup
change that doesn't fix anything.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
It was left unnoticed by accident, which means that the code could be
cleaned up a tad more.Acked-by: Jon Hunter
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
The clocksource rate is initialized only for the first per-CPU clocksource
and then that rate shall be replicated for the rest of clocksource's
because they are initialized manually in the code.Fixes: 3be2a85a0b61 ("clocksource/drivers/tegra: Support per-CPU timers on all Tegra's")
Acked-by: Jon Hunter
Tested-by: Jon Hunter
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
Rename driver's source file to better reflect that it's not specific to
older SoC generations.Suggested-by: Daniel Lezcano
Signed-off-by: Dmitry Osipenko
Acked-By: Peter De Schrijver
Signed-off-by: Daniel Lezcano
