28 Apr, 2020
1 commit
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This patch adds support for performance reporting private feature
for FPGA Management Engine (FME). Now it supports several different
performance counters, including 'basic', 'cache', 'fabric', 'vtd'
and 'vtd_sip'. It allows user to use standard linux tools to access
these performance counters.e.g. List all events by "perf list"
perf list | grep fme
dfl_fme0/cache_read_hit/ [Kernel PMU event]
dfl_fme0/cache_read_miss/ [Kernel PMU event]
...dfl_fme0/fab_mmio_read/ [Kernel PMU event]
dfl_fme0/fab_mmio_write/ [Kernel PMU event]
...dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event]
dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event]
...dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event]
dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event]
...dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event]
dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event]
...dfl_fme0/clock [Kernel PMU event]
...e.g. check increased counter value after run one application using
"perf stat" command.perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test
Performance counter stats for './test':
1 dfl_fme0/fab_mmio_read/
2 dfl_fme0/fab_mmio_write/1.009496520 seconds time elapsed
Please note that fabric counters support both fab_* and fab_port_*, but
actually they are sharing one set of performance counters in hardware.
If user wants to monitor overall data events on fab_* then fab_port_*
can't be supported at the same time, see example below:perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/
Performance counter stats for 'system wide':
0 dfl_fme0/fab_mmio_read/
dfl_fme0/fab_port_mmio_write,portid=0/2.141064085 seconds time elapsed
Signed-off-by: Luwei Kang
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.com
Signed-off-by: Greg Kroah-Hartman
04 Sep, 2019
2 commits
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This patch adds support for global error reporting for FPGA
Management Engine (FME), it introduces sysfs interfaces to
report different error detected by the hardware, and allow
user to clear errors or inject error for testing purpose.Signed-off-by: Luwei Kang
Signed-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer -
Error reporting is one important private feature, it reports error
detected on port and accelerated function unit (AFU). It introduces
several sysfs interfaces to allow userspace to check and clear
errors detected by hardware.Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
15 Apr, 2019
1 commit
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This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.Signed-off-by: Nava kishore Manne
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Michal Simek
27 Nov, 2018
1 commit
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Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel service layer driver
which does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.Signed-off-by: Alan Tull
Signed-off-by: Richard Gong
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
15 Jul, 2018
10 commits
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DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to
unmap it after use, otherwise, driver will unmap them in device file
release operation.Each AFU has its own rb tree to keep track of its mapped DMA regions.
Ioctl interfaces:
* DFL_FPGA_PORT_DMA_MAP
Do the dma mapping per user_addr and length provided by user.
Return iova in provided struct dfl_fpga_port_dma_map.* DFL_FPGA_PORT_DMA_UNMAP
Unmap the dma region per iova provided by user.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid PR bitstream is programmed and the port is enabled,
then this MMIO region could be accessed.This patch adds support to enumerate the AFU MMIO region and expose it
to userspace via mmap file operation. Below interfaces are exposed to user:Sysfs interface:
* /sys/class/fpga_region///afu_id
Read-only. Indicate which PR bitstream is programmed to this AFU.Ioctl interfaces:
* DFL_FPGA_PORT_GET_INFO
Provide info to userspace on the number of supported region.
Only UAFU region is supported now.* DFL_FPGA_PORT_GET_REGION_INFO
Provide region information, including access permission, region size,
offset from the start of device fd.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
infrastructure (static FPGA region) via a Port. Port CSRs are
implemented separately from the AFU CSRs to provide control and
status of the Port. Once valid PR bitstream is programmed into
the AFU, it allows access to the AFU CSRs in the AFU MMIO space.This patch only implements basic driver framework for AFU, including
device file operation framework.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set callback for fpga bridge.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
and invokes fpga-region's interface (fpga_region_program_fpga) for PR
operation once PR request received via ioctl. Below user space interface
is exposed by this sub feature.Ioctl interface:
* DFL_FPGA_FME_PORT_PR
Do partial reconfiguration per information from userspace, including
target port(AFU), buffer size and address info. It returns error code
to userspace if failed. For detailed PR error information, user needs
to read fpga-mgr's status sysfs interface.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device created by
DFL framework.This patch adds the basic framework of FME platform driver. It defines
sub feature drivers to handle the different sub features, including init,
uinit and ioctl. It also registers the file operations for the device file.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch implements the basic framework of the driver for FPGA PCIe
device which implements the Device Feature List (DFL) in its MMIO space.
This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including
both integrated (e.g. Intel Server Platform with In-package FPGA) and
discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Device Feature List (DFL) defines a feature list structure that creates
a linked list of feature headers within the MMIO space to provide an
extensible way of adding features. This patch introduces a kernel module
to provide basic infrastructure to support FPGA devices which implement
the Device Feature List.Usually there will be different features and their sub features linked into
the DFL. This code provides common APIs for feature enumeration, it creates
a container device (FPGA base region), walks through the DFLs and creates
platform devices for feature devices (Currently it only supports two
different feature devices, FPGA Management Engine (FME) and Port which
the Accelerator Function Unit (AFU) connected to). In order to enumerate
the DFLs, the common APIs required low level driver to provide necessary
enumeration information (e.g. address for each device feature list for
given device) and fill it to the dfl_fpga_enum_info data structure. Please
refer to below description for APIs added for enumeration.Functions for enumeration information preparation:
*dfl_fpga_enum_info_alloc
allocate enumeration information data structure.*dfl_fpga_enum_info_add_dfl
add a device feature list to dfl_fpga_enum_info data structure.*dfl_fpga_enum_info_free
free dfl_fpga_enum_info data structure and related resources.Functions for feature device enumeration:
*dfl_fpga_feature_devs_enumerate
enumerate feature devices and return container device.*dfl_fpga_feature_devs_remove
remove feature devices under given container device.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
23 Apr, 2018
1 commit
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This patch adds support to the FPGA manager for programming
MachXO2 device’s internal flash memory, via slave SPI.Signed-off-by: Paolo Pisati
[atull@kernel.org: use existing FPGA mgr API]
Signed-off-by: Alan Tull
Signed-off-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
28 Nov, 2017
1 commit
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Create of-fpga-region.c and move the following functions without
modification from fpga-region.c.* of_fpga_region_find
* of_fpga_region_get_mgr
* of_fpga_region_get_bridges
* child_regions_with_firmware
* of_fpga_region_parse_ov
* of_fpga_region_notify_pre_apply
* of_fpga_region_notify_post_remove
* of_fpga_region_notify
* of_fpga_region_probe
* of_fpga_region_removeCreate two new functions with some code from fpga_region_init/exit.
* of_fpga_region_init
* of_fpga_region_exitSigned-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
02 Nov, 2017
1 commit
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Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.By default all files without license information are under the default
license of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if
Reviewed-by: Philippe Ombredanne
Reviewed-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
17 Jul, 2017
2 commits
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Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
and Arria-10 FPGAs via CvP.Signed-off-by: Anatolij Gustschin
Reviewed-by: Andy Shevchenko
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.Signed-off-by: Joshua Clayton
Signed-off-by: Anatolij Gustschin
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
08 Apr, 2017
4 commits
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This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.Signed-off-by: Moritz Fischer
Signed-off-by: Michal Simek
Cc: Sören Brinkmann
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.Signed-off-by: Matthew Gerlach
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component. It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.Signed-off-by: Matthew Gerlach
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The driver loads FPGA firmware over SPI, using the "slave serial"
configuration interface on Xilinx FPGAs.Signed-off-by: Anatolij Gustschin
Acked-by: Michal Simek
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
17 Mar, 2017
2 commits
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This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.Signed-off-by: Joel Holdsworth
Reviewed-by: Marek Vasut
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.Signed-off-by: Florian Fainelli
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
11 Nov, 2016
5 commits
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Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.Signed-off-by: Alan Tull
Reviewed-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge
framework. A freeze bridge is a bridge that exists in the FPGA
fabric to isolate one region of the FPGA from the busses while that
one region is being reprogrammed.Signed-off-by: Alan Tull
Signed-off-by: Matthew Gerlach
Signed-off-by: Greg Kroah-Hartman -
Supports Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpgaAllows enabling/disabling the bridges through the FPGA
Bridge Framework API functions.The fpga2sdram driver only supports enabling and disabling
of the ports that been configured early on. This is due to
a hardware limitation where the read, write, and command
ports on the fpga2sdram bridge can only be reconfigured
while there are no transactions to the sdram, i.e. when
running out of OCRAM before the kernel boots.Device tree property 'init-val' configures the driver to
enable or disable the bridge during probe. If the property
does not exist, the driver will leave the bridge in its
current state.Signed-off-by: Alan Tull
Signed-off-by: Matthew Gerlach
Signed-off-by: Dinh Nguyen
Signed-off-by: Greg Kroah-Hartman -
FPGA Regions support programming FPGA under control of the Device
Tree.Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This framework adds API functions for enabling/
disabling FPGA bridges under kernel control.This allows the Linux kernel to disable FPGA bridges
during FPGA reprogramming and to enable FPGA bridges
when FPGA reprogramming is done. This framework is
be manufacturer-agnostic, allowing it to be used in
interfaces that use the FPGA Manager Framework to
reprogram FPGA's.The functions are:
* of_fpga_bridge_get
* fpga_bridge_put
Get/put an exclusive reference to a FPGA bridge.* fpga_bridge_enable
* fpga_bridge_disable
Enable/Disable traffic through a bridge.* fpga_bridge_register
* fpga_bridge_unregister
Register/unregister a device-specific low level FPGA
Bridge driver.Get an exclusive reference to a bridge and add it to a list:
* fpga_bridge_get_to_listTo enable/disable/put a set of bridges that are on a list:
* fpga_bridges_enable
* fpga_bridges_disable
* fpga_bridges_putSigned-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
18 Oct, 2015
1 commit
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This commit adds FPGA Manager support for the Xilinx Zynq chip.
The code borrows some from the xdevcfg driver in Xilinx'
vendor tree.Signed-off-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
08 Oct, 2015
2 commits
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Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.Signed-off-by: Alan Tull
Acked-by: Michal Simek
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
API to support programming FPGA's.
The following functions are exported as GPL:
* fpga_mgr_buf_load
Load fpga from image in buffer* fpga_mgr_firmware_load
Request firmware and load it to the FPGA.* fpga_mgr_register
* fpga_mgr_unregister
FPGA device drivers can be added by calling
fpga_mgr_register() to register a set of
fpga_manager_ops to do device specific stuff.* of_fpga_mgr_get
* fpga_mgr_put
Get/put a reference to a fpga manager.The following sysfs files are created:
* /sys/class/fpga_manager//name
Name of low level driver.* /sys/class/fpga_manager//state
State of fpga managerSigned-off-by: Alan Tull
Acked-by: Michal Simek
Signed-off-by: Greg Kroah-Hartman