Eric Lee / smarc-fsl-linux-kernel

09 May, 2007

3 commits

08 Feb, 2007

2 commits

09 Jan, 2007

1 commit

  • 6020dff09   [ARM] Resolve fuse and direct-IO failures due to missing cache flushes ... Browse Code »

    fuse does not work on ARM due to cache incoherency issues - fuse wants
    to use get_user_pages() to copy data from the current process into
    kernel space. However, since this accesses userspace via the kernel
    mapping, the kernel mapping can be out of date wrt data written to
    userspace.

    This can lead to unpredictable behaviour (in the case of fuse) or data
    corruption for direct-IO.

    This resolves debian bug #402876

    Signed-off-by: Russell King

    Russell King
     

31 Dec, 2006

1 commit

  • 1c9d3df5e   [ARM] 4078/1: Fix ARM copypage cache coherency problems ... Browse Code »

    If PG_dcache_dirty is set for a page, we need to flush the source page
    before performing any copypage operation using a different virtual address.

    This fixes the copypage implementations for XScale, StrongARM and ARMv6.

    This patch fixes segmentation faults seen in the dynamic linker under
    the usage patterns in glibc 2.4/2.5.

    Signed-off-by: Richard Purdie
    Signed-off-by: Russell King

    Richard Purdie
     

14 Dec, 2006

1 commit

  • ec8c0446b   [PATCH] Optimize D-cache alias handling on fork ... Browse Code »

    Virtually index, physically tagged cache architectures can get away
    without cache flushing when forking. This patch adds a new cache
    flushing function flush_cache_dup_mm(struct mm_struct *) which for the
    moment I've implemented to do the same thing on all architectures
    except on MIPS where it's a no-op.

    Signed-off-by: Ralf Baechle
    Signed-off-by: Linus Torvalds

    Ralf Baechle
     

28 Sep, 2006

6 commits

03 Sep, 2006

1 commit

  • a188ad2bc   [ARM] 3762/1: Fix ptrace cache coherency bug for ARM1136 VIPT nonaliasing Harvard caches ... Browse Code »

    Patch from George G. Davis

    Resolve ARM1136 VIPT non-aliasing cache coherency issues observed when
    using ptrace to set breakpoints and cleanup copy_{to,from}_user_page()
    while we're here as requested by Russell King because "it's also far
    too heavy on non-v6 CPUs".

    NOTES:

    1. Only access_process_vm() calls copy_{to,from}_user_page().
    2. access_process_vm() calls get_user_pages() to pin down the "page".
    3. get_user_pages() calls flush_dcache_page(page) which ensures cache
    coherency between kernel and userspace mappings of "page". However
    flush_dcache_page(page) may not invalidate I-Cache over this range
    for all cases, specifically, I-Cache is not invalidated for the VIPT
    non-aliasing case. So memory is consistent between kernel and user
    space mappings of "page" but I-Cache may still be hot over this
    range. IOW, we don't have to worry about flush_cache_page() before
    memcpy().
    4. Now, for the copy_to_user_page() case, after memcpy(), we must flush
    the caches so memory is consistent with kernel cache entries and
    invalidate the I-Cache if this mm region is executable. We don't
    need to do anything after memcpy() for the copy_from_user_page()
    case since kernel cache entries will be invalidated via the same
    process above if we access "page" again. The flush_ptrace_access()
    function (borrowed from SPARC64 implementation) is added to handle
    cache flushing after memcpy() for the copy_to_user_page() case.

    Signed-off-by: George G. Davis
    Signed-off-by: Russell King

    George G. Davis
     

26 Apr, 2006

1 commit

29 Mar, 2006

1 commit

  • 23bdf86aa   [ARM] 3377/2: add support for intel xsc3 core ... Browse Code »

    Patch from Lennert Buytenhek

    This patch adds support for the new XScale v3 core. This is an
    ARMv5 ISA core with the following additions:

    - L2 cache
    - I/O coherency support (on select chipsets)
    - Low-Locality Reference cache attributes (replaces mini-cache)
    - Supersections (v6 compatible)
    - 36-bit addressing (v6 compatible)
    - Single instruction cache line clean/invalidate
    - LRU cache replacement (vs round-robin)

    I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
    cores have separate errata and have to handle things like L2, so it
    is simpler to keep it separate.

    L2 cache support is currently a build option because the L2 enable
    bit must be set before we enable the MMU and there is no easy way to
    capture command line parameters at this point.

    There are still optimizations that can be done such as using LLR for
    copypage (in theory using the exisiting mini-cache code) but those
    can be addressed down the road.

    Signed-off-by: Deepak Saxena
    Signed-off-by: Lennert Buytenhek
    Signed-off-by: Russell King

    Lennert Buytenhek
     

04 Jan, 2006

1 commit

  • 78ff18a41   [ARM] Cleanup ARM includes ... Browse Code »

    arch/arm/kernel/entry-armv.S has contained a comment suggesting
    that asm/hardware.h and asm/arch/irqs.h should be moved into the
    asm/arch/entry-macro.S include. So move the includes to these
    two files as required.

    Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h
    includes which use those facilities, and remove asm/io.h from
    kernel/process.c.

    Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm
    and arch/arm/mach-footbridge.

    Signed-off-by: Russell King

    Russell King
     

08 Sep, 2005

1 commit

20 Jun, 2005

1 commit

17 Apr, 2005

1 commit

  • 1da177e4c   Linux-2.6.12-rc2 ... Browse Code »

    Initial git repository build. I'm not bothering with the full history,
    even though we have it. We can create a separate "historical" git
    archive of that later if we want to, and in the meantime it's about
    3.2GB when imported into git - space that would just make the early
    git days unnecessarily complicated, when we don't have a lot of good
    infrastructure for it.

    Let it rip!

    Linus Torvalds