Eric Lee / smarc-fsl-linux-kernel

13 Oct, 2017

1 commit

  • 24ea78a09   clk: sunxi-ng: sun8i: a23: Use sigma-delta modulation for audio PLL ... Browse Code »

    The audio blocks require specific clock rates. Until now we were using
    the closest clock rate possible with integer N-M factors. This resulted
    in audio playback being slightly slower than it should be.

    The vendor kernel gets around this (for newer SoCs) by using sigma-delta
    modulation to generate a fractional-N factor. As the PLL hardware is
    identical in most chips, we can back port the settings from the newer
    SoC, in this case the H3, onto the A23.

    Signed-off-by: Chen-Yu Tsai
    Signed-off-by: Maxime Ripard

    Chen-Yu Tsai
     

22 Jul, 2017

1 commit

  • 166739312   clk: Convert to using %pOF instead of full_name ... Browse Code »

    Now that we have a custom printf format specifier, convert users of
    full_name to use %pOF instead. This is preparation to remove storing
    of the full path string for each node.

    Signed-off-by: Rob Herring
    Cc: Michael Turquette
    Cc: Stephen Boyd
    Cc: Maxime Coquelin
    Cc: Alexandre Torgue
    Cc: Russell King
    Cc: Matthias Brugger
    Cc: Geert Uytterhoeven
    Cc: Maxime Ripard
    Cc: Chen-Yu Tsai
    Cc: "Emilio López"
    Cc: Peter De Schrijver
    Cc: Prashant Gaikwad
    Cc: Thierry Reding
    Cc: Jonathan Hunter
    Cc: Tero Kristo
    Cc: linux-clk@vger.kernel.org
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-mediatek@lists.infradead.org
    Cc: linux-renesas-soc@vger.kernel.org
    Cc: linux-tegra@vger.kernel.org
    Cc: linux-omap@vger.kernel.org
    Acked-by: Maxime Ripard
    Reviewed-by: Geert Uytterhoeven
    Acked-by: Geert Uytterhoeven
    Acked-by: James Liao
    Acked-by: Alexandre TORGUE
    Reviewed-by: Matthias Brugger
    Signed-off-by: Stephen Boyd

    Rob Herring
     

07 Jun, 2017

1 commit

  • 13e0dde8b   clk: sunxi-ng: Support multiple variable pre-dividers ... Browse Code »

    On the A83T, the AHB1 clock has a shared pre-divider on the two
    PLL-PERIPH clock parents. To support such instances of shared
    pre-dividers, this patch extends the mux clock type to support
    multiple variable pre-dividers.

    As the pre-dividers are only used to calculate the rate, but
    do not participate in the factorization process, this is fairly
    straightforward.

    Signed-off-by: Chen-Yu Tsai
    Signed-off-by: Maxime Ripard

    Chen-Yu Tsai
     

12 Nov, 2016

1 commit

  • 937ff9ded   clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks ... Browse Code »

    The audio module clocks are supposed to be set according to the sample
    rate of the audio stream. The audio PLL provides the clock signal for
    these module clocks, and only it is freely tunable.

    Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
    properly tune the clock rate.

    Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU")
    Signed-off-by: Chen-Yu Tsai
    Signed-off-by: Maxime Ripard

    Chen-Yu Tsai
     

21 Sep, 2016

1 commit

10 Sep, 2016

1 commit

  • 5690879d9   clk: sunxi-ng: Add A23 CCU ... Browse Code »

    Add support for the clock unit found in the A23. Due to the similarities
    with the A33, it also shares its clock IDs to allow sharing the DTSI.

    Signed-off-by: Maxime Ripard
    Acked-by: Chen-Yu Tsai

    Maxime Ripard