06 Jul, 2016
2 commits
-
of_node_put needs to be called when the device node which is got
from of_parse_phandle has finished using.[Commit updated to fix an error by MyungJoo]
Cc: Chanwoo Choi
Cc: MyungJoo Ham
Cc: Kyungmin Park
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Signed-off-by: Peter Chen
Acked-by: Chanwoo Choi
Signed-off-by: MyungJoo Ham -
In case of exynos_bus_parse_of() failure the code shouldn't
try to remove the OPP table and disable+unprepare bus->clk
as it has been already handled in exynos_bus_parse_of().Signed-off-by: Bartlomiej Zolnierkiewicz
Acked-by: Chanwoo Choi
Signed-off-by: MyungJoo Ham
03 May, 2016
3 commits
-
- Typo in comments fixed
- Unnecessary return statement removedSigned-off-by: MyungJoo Ham
-
This patch adds the support of bus frequency feature for sub-blocks which share
the one power line. If each bus depends on the power line, each bus is not able
to change the voltage by oneself. To optimize the power-consumption on runtime,
some buses using the same power line should change the source clock and
regulator at the same time. So, this patch uses the passive governor to support
the bus frequency for all buses which sharing the one power line.For example,
Exynos3250 include the two power line for AXI buses as following:
: VDD_MIF : MIF (Memory Interface) provide the DMC (Dynamic Memory Controller)
with the power (regulator).
: VDD_INT : INT (Internal) provide the various sub-blocks with the power
(regulator).Each bus is included in as follwoing block. In the case of VDD_MIF, only DMC bus
use the power line. So, there is no any depencency between buese. But, in the
case of VDD_INT, various buses share the one power line of VDD_INT. We need to
make the depenency between buses. When using passive governor, there is no
problem to support the bus frequency as DVFS for all buses. One bus should be
operated as the parent bus device which gathering the current load of INT block
and then decides the new frequency with some governors except of passive
governor. After deciding the new frequency by the parent bus device, the rest
bus devices will change the each source clock according to new frequency of the
parent bus device.- MIF (Memory Interface) block
: VDD_MIF |--- DMC- INT (Internal) block
: VDD_INT |--- LEFTBUS (parent)
|--- PERIL
|--- MFC
|--- G3D
|--- RIGHTBUS
|--- FSYS
|--- LCD0
|--- PERIR
|--- ISP
|--- CAMSigned-off-by: Chanwoo Choi
[tjakobi: Reported debugfs error during booting and cw00.choi fix it.]
Reported-by: Tobias Jakobi
Signed-off-by: MyungJoo Ham
Acked-by: Krzysztof Kozlowski -
This patch adds the generic exynos bus frequency driver for AMBA AXI bus
of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
have the common architecture for bus between DRAM and sub-blocks in SoC.
This driver can support the generic bus frequency driver for Exynos SoCs.In devicetree, Each bus block has a bus clock, regulator, operation-point
and devfreq-event devices which measure the utilization of each bus block.Signed-off-by: Chanwoo Choi
[m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board]
Tested-by: Markus Reichl
Tested-by: Anand Moon
Signed-off-by: MyungJoo Ham
Acked-by: Krzysztof Kozlowski
