08 Jun, 2017
40 commits
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Add a binding document for lpi2c driver.
Signed-off-by: Gao Pan
Signed-off-by: Wolfram Sang -
There is no card-detection pad connected for sd3 on the i.mx6 SX
EVB board. The card is assumed to be non-removable, hence, there is
no need to redetect the card during the pm callbacks. This can be
reached by including the pm-ignore-notify option on the usdhc3 device
on the dtb file.Signed-off-by: Juan Gutierrez
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The usb otg2, on the SXSCM EVB board is powered up directly by the
GEN_V5 signal from the PMIC, so there is no gpio assigned.The wrong assignation was preventing the busfreq driver to switch
to any other frequency, since the usb otg2 looks to be always
active.Signed-off-by: Juan Gutierrez
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Using the mdio and ethphy device that is referenced as a phy_handle
by the fec device is not properly handling the resume from suspend.Signed-off-by: Juan Gutierrez
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BCM WiFi driver needs to take care of card detect by itself. Using cd-post
property tells the mmc core to not detect the card automatically during
host driver probe and post it untill the client driver notifies to do it.The non-removable option is also required to fix a NULL dereference
occurred when resuming from suspend. The pm-ignore-notify parameter is
also included.Signed-off-by: Juan Gutierrez
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Disable i.MX7ULP's IOMUXC now since there is no module
using it and after kernel boot up, below failed message
will come out:imx7ulp-pinctrl 4103d000.iomuxc: fail to probe dt properties
imx7ulp-pinctrl: probe of 4103d000.iomuxc failed with error -22Any module who needs it can enable it anytime.
Signed-off-by: Anson Huang
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Update i.MX7ULP SOM board LPDDR3 script according to
u-boot script change.Signed-off-by: Anson Huang
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i.MX7ULP's lpuart4 is disabled in dtsi, need to enable it in
14x14 arm2 board for console.Signed-off-by: Anson Huang
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Add oob support for imx6sll sdio wifi to improve
the performance.Signed-off-by: Gao Pan
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CONFIG_FHANDLE=y is needed when running
systemd with version >=210, so that it can
spawn a serial tty via getty.Signed-off-by: Nitin Garg
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Enable eDMA by default.
Signed-off-by: Fugang Duan
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- correct DMAMUX enable bit.
- correct mapping the DMAMUX source and slot.Signed-off-by: Fugang Duan
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Remove the lpuart6 dummy node.
Signed-off-by: Fugang Duan
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Add Murata 1DX wifi/bt for evk board.
Signed-off-by: Fugang Duan
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Add fw/nv path parse from dts support to support multiple modules
with build in.Signed-off-by: Fugang Duan
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SAI input select value is not correct for some pins. This patch
is to correct these valuesSigned-off-by: Shengjiu Wang
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Calculate the rela count for the case that eDMA stop after get eeop signal.
Signed-off-by: Fugang Duan
Signed-off-by: Robin Gong -
Updated the edma driver to support edma2 on ULP1.
Signed-off-by: Shenwei Wang
Signed-off-by: Robin Gong -
When resuming from VLLS mode, the wdog will be reset, the first we configure
the wdog, an initial timeout value should be write into the TOVAL register,
otherwise, the wdog will not be initialized successfully.Signed-off-by: Bai Ping
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Add i.MX7ULP 14x14 arm2 board support.
Signed-off-by: Anson Huang
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There are 2 usdhc instances on i.MX7ULP, previous
usdhc1 should be usdhc0, now add the correct usdhc1 node.Signed-off-by: Anson Huang
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Add gpio port control clocks, and add them to init table.
If the gpio clock is controlled by gpio driver, the watchdog
reset will occur due to unknown reason, we need to debug it
if we need driver to control its clocks.Signed-off-by: Peter Chen
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On i.MX7ULP, the IOMUXC PAD register has IBE and OBE bit to control
the input/output buffer if a PIN wants to use as GPIO function.Additonally, on i.MX7ULP, the MUX reg and CONFIG reg is shared in one
register and the GPIO function select in the MUX is not index zero as
on I.MX6 SOC, add support in code for i.MX7ULP GPIO function.Signed-off-by: Bai Ping
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
Add GPIO (PCTLC,D,E,F) support
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
Add direction set for mx7ulp.
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
In commit: b1a04e6ed63,(MLK-13413), the tempmon node is
wrongly disabled. so fix it in this patch.Signed-off-by: Bai Ping
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Enable wdog driver in defconfig.
Signed-off-by: Bai Ping
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When the wdog driver is added for i.MX7ULP, it is no need to
do wdog driver disable when resume from VLLS mode as wdog driver
will handle it.Signed-off-by: Bai Ping
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Add watchdog driver for i.MX7ULP.
Signed-off-by: Bai Ping
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Add 'timeout-sec' property for wdog node of i.MX7ULP.
Signed-off-by: Bai Ping
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Improve the fractional divider calculation accuracy use
continued fraction method.Signed-off-by: Bai Ping
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RBB needs to be enabled for VLPS mode to save
power, it can save ~0.4mA on VDD_DIG1.Signed-off-by: Anson Huang
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Add RTC node for i.MX7ULP, re-use SNVS RTC.
Signed-off-by: Anson Huang
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On i.MX7ULP, there are options to select SPLL or SPLL PFD
as SPLL output clock SPLL_SEL, so the SPLL option for
sys_sel mux should be from SPLL_SEL, NOT from SPLL directly.Previous:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 2 2 531648000 0
sys_sel 1 1 531648000 0
core_div 2 2 531648000 0
plat_div 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 1 1 503666526 0
spll_pfd_sel 0 0 503666526 0
spll_sel 0 0 503666526 0
After fixed:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 2 2 503666526 0
spll_pfd_sel 1 1 503666526 0
spll_sel 1 1 503666526 0
sys_sel 1 1 503666526 0
core_div 1 1 503666526 0
plat_div 1 1 503666526 0CORE_DIV clock will be enabled automatically when PLAT_DIV
is enabled, so we can skip it in clks_init_on.Now that sys_sel clock tree is correct, no need to have SPLL_PFD0
in clks_init_on, as it will be enabled automatically because of
PLAT_DIV.Signed-off-by: Anson Huang
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Per design request, all PLLs/PFDs need to be disabled before
entering low power mode, here for VLPS/VLLS mode, add this
procedure.For VLPS mode, DDR is also in self-refresh mode, so NVCC_DRAM_SW
can be turned off as well, add this support.Signed-off-by: Anson Huang
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change parent clock to pll3_pfd2 and calculate out a desired pixel clock
rate. This patch fixed the following warning.
"imx_epdc_v2_fb 20f4000.epdc: Unable to get an accurate EPDC pix clkdesired = 40000000, actual = 63529412"Signed-off-by: Robby Cai
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Add eMMC support (8 bit mode) for ulp-evk board.
Signed-off-by: Haibo Chen
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When enter VLLS mode, DRAM is in self-refresh, NVCC_DRAM_SW
can be off to save power.As the static io-map formula is no longer feasible on i.MX7ULP,
here we change it to ioremap for creating iram tlb.Remove the physical module base address in pm_info structure
to save iram space.Signed-off-by: Anson Huang
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Add PTC1 pin as GPIO on i.MX7ULP SOM board, it is
to control NVCC_DRAM_SW during suspend/resume.Signed-off-by: Anson Huang
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Support i.MX6SLL OTP.
There are 4 works in bank7/bank8.
When read, use address offset.
When prog, use bank/index, note that bank7/bank8 we treat
them a single bank when prog.Tested GP41 and GP31 read/write on eng sample chip.
Signed-off-by: Peng Fan
(cherry picked from commit f8698b66fcbec7409b738a4c5b05ba87f0342cf8)