26 Feb, 2019
4 commits
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Update domu car dts according to android auto changes.
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
When resources are owned by M41, we need to handle that correctly in
xen.Also drop power doamins for xen,shared gpio, xen will power up the gpio.
gpio1 is owned by M41, so we also need to check its power status in xen.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
CM41 runs before CortexA, we should not use smmu to restrict it, because
smmu is owned by xen. Also remove MU_13/12 which is wrongly added
before.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
reduce the time that open operation spent,
allocate the buffer when neededSigned-off-by: ming_qian
25 Feb, 2019
3 commits
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mode
Can't set mode like loopback,listen-only and so on due to wrong setting when
enable ISO-FD mode.Signed-off-by: Joakim Zhang
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kernel process(with zero pid) has no mdl mapping,
skip kernel process to avoid invalid mdl access.also remove memory barrier to avoid rcu issue.
Signed-off-by: Xianzhong
(cherry picked from commit 5ced43c64b88fb4c6106fa295dc7e55a1a5c7bef) -
The hdmi_drm_infoframe_pack() was wrongly packing the HDR metadata. It
was setting the x display primaries followed by the y display primaries.
Instead, in the specifications, each x display primary should be
followed by the corresponding y display primary.Also, byte 8 of the frame payload was being skipped. Fixed that too.
Signed-off-by: Laurentiu Palcu
Reported-by: Jared Hu
23 Feb, 2019
4 commits
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change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.Signed-off-by: Han Xu
(cherry picked from commit f55654688059a337490915cd6f652d0585597f3d) -
Add delay cell support for fspi to set calibrated value to DLL register
for different clock frequency.Signed-off-by: Han Xu
(cherry picked from commit 5b608b98697668bd11563febba89bd0eea1c1b26) -
Several code changes to improve the i.MX8MM fspi performance.
- Implemented the SFDP lut to get the correct chip information
- Changed the default read mode from normal read to Quad DDR
- Enabled the AHB prefetch after chip probed
- Limited the highest clock rate for iMX8MMSigned-off-by: Han Xu
(cherry picked from commit c8dfe6ab108909a2e5bbc0ec11f3a24ad5b5844d) -
Increased the clock rate for better performance.
Signed-off-by: Han Xu
(cherry picked from commit 582ba08afcaf79fc09465a0cd2dd66cf1e86813e)
22 Feb, 2019
10 commits
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After fix the ADMA length mismatch issue on imx8mm, we can
support eMMC CMDQ, so enable it. This patch also make imx8mm
support HS400ES mode.Signed-off-by: Haibo Chen
(cherry picked from commit 861d1d962e90f1244bfc8249d111c633c9c038ca) -
After system suspend, CQE is in cqhci_off state, which set the HALT bit, make
CQE in HALT state. If the SoC do not power down the USDHC module, then when
system resume back, this bit keep the same, still set. So need to clear this
bit when enable CQE for the first request after system resume back. If not,
imx8mm will stuck in the first CMDQ request after system resume back. On
imx8qxp and imx8qm, we do not find this issue because usdhc module lost power
during system suspend/resume, and all the register return to the default reset
value, and the reset value of bit HALT is 0.Signed-off-by: Haibo Chen
(cherry picked from commit 49d6f5d5cca3a66fa65568a50f75cbbac87ba312) -
the commit 885c943ca13d ("ENGR00288842 mmc: sdhci-esdhc-imx: add
ADMA Length Mismatch errata fix") involve the fix of ERR004536.
But double confirm with IC, need to clear the bit 7 of register
0x6c rather than set this bit 7.
here is the function of bit 7 of 0x6c:
0: enable the new IC fix for ERR004536
1: do not use the IC fix, keep the same as beforeDue to the reset value of this bit 7 is 0, and ROM code also do not
touch this bit 7, so this patch directly remove the operation of this
bit 7, make sure the fix of ERR004536 can work.Note, for all versons of 6DQP 6DQ 6DL and 6SL, IC do not has this
hardware fix, so writing this bit has no effect and we keep using
ADMA as before which has been used for several years with the
consideration of no performance drop.For other SoC like imx6SLL imx6SX imx6UL/imx6ULL imx7 imx8, IC already
contain this hareware fix, so must make sure the bit 7 of the register
0x6c is 0. If not, we meet the ADMA length mismatch error on imx8mm-evk
and imx8qxp-ddr3l-val board when enable CMDQ.Signed-off-by: Haibo Chen
(cherry picked from commit 2ea2f2b374545ff63a714fabc16c0d7c6b3b47b6) -
the data is invalid in first read for dma registers,
add second read to get the correct register data.Signed-off-by: Xianzhong
(cherry picked from commit 90ee1cbacb7794eb4db0cfa0e8b6d0bb2ed45bf6) -
The default watchdog action is partition reset now, so no need kernel
to take care. Besides, scfw full test case may set other watchdog
action but kernel may set it back later to default partition reset
which scfw wouldn't expect, so avoid touching watchdog action.
Please modify scfw code in case changing watchdog action to board
reset.Signed-off-by: Robin Gong
Reviewed-by: Anson Huang -
Add new dts and dtsi file for virtual i2c driver on i.MX8QXP and i.MX8QM
board.Merge fsl-imx8qm/8qxp-mek-m4.dts to fsl-imx8qm/8qxp-mek-rpmsg.dtsi. So
delete these two files.Signed-off-by: Clark Wang
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Enable RPBUS(i2c-rpmsg-imx.c) and RPMSG functions.
Signed-off-by: Clark Wang
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cs42xx8 will call regcache_sync to refresh its register cache. However,
it will send a long msg which length is greater than the max buffer size
of virtual i2c driver. It will cause the regcache_sync operation failed.
So, use the single read/write to send i2c msg in regcache functions.Signed-off-by: Clark Wang
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For the virtual i2c driver should be initialized in subsystem before the
other modules initialize. So, the imx_rpmsg and virtio_rpmsg_bus should
be initialized before virtual i2c driver. Now, use arch_initcall to
initialize these two modules.Signed-off-by: Clark Wang
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Add virtual i2c driver to send SRTM i2c messages to M4.
Each virtual I2C bus has a specal bus id, which is abstracted by M4.
Each SRTM message include a bus id for the bus which the device is on.Virtual i2c rpmsg bus will bind rpbus nodes with compatible string
"fsl,i2c-rpbus". And "rpmsg-i2c-channel" will probe only one rpmsg
channel for all rpbuses.This virtual i2c driver depends on CONFIG_I2C and CONFIG_RPMSG.
Signed-off-by: Clark Wang
21 Feb, 2019
4 commits
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Need to check the content protection property first in
imx_hdp_imx_encoder_enable. The function may return if
drm_hdmi_infoframe_set_hdr_metadata returns an error. This was preventing
iMX8QM from enabling content protection.Signed-off-by: Oliver Brown
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IR uses GPIO1_13 not GPIO_12 in imx8mm-evk board.
Signed-off-by: Joakim Zhang
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Some test cases need to use RTC driver data, so do NOT
overwrite it using rpmsg data structure.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
(cherry picked from commit da74fb3d328f037ecb1832a53f45cebdbda8f86f) -
When do dpu blit and wait to finish, it will call usleep_range(10, 20)
to poll register state. Change to usleep_range(30, 50) to low down CPU loading.Change-Id: If84c436b31d228b8b7a2a41e89611d354270baba
Signed-off-by: Ivan.liu
20 Feb, 2019
5 commits
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When system enters VLPS/VLLS mode, the IOMUXC config register
for MMDC related IO pads need to set to '0' to reduce the current
leakage for these IO pads.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang -
Audio PLL is a frac pll, the config for this PLL should follow
below limitation:
Fout = ((m + k / 65536) * FIN) / (p * 2^s),
Fvco = ((m + k / 65536) * FIN) / p
Fref = FIN / pa). 6MHz
Reviewed-by: Anson Huang
(cherry picked from commit 9a774f3e8bfce2fcd2472b8656f84a452276a7a8) -
Set IR built-in on imx8 boards.
Signed-off-by: Joakim Zhang
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Enable IR on imx8mq-evk board.
Signed-off-by: Joakim Zhang
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Enable IR on imx8mm-evk board.
Signed-off-by: Joakim Zhang
19 Feb, 2019
2 commits
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The following commit:
459a5fac54d - MLK-20263: drm/imx/dcss: fix channel-0 line shift
removed the 5 tap filter for vertical luma/chroma when YUV formats were
used.Problem is that when the 7 tap filter is used for vertical luma/chroma,
artifacts can be seen on screen when scaling.RGB can, however, function correctly with only 7 tap filter.
This patch partially reverts the above patch and also does some cosmetic
changes when calling the dcss_scaler_filter_design() using false/true
instead of 0/1 for use_5_taps argument.Signed-off-by: Laurentiu Palcu
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i.MX8QXP has separated irq, and shared irq for lpuart with eDMA,
it is better for uart to use separated irq although there has
no function impact.Reviewed-by: Robin Gong
Signed-off-by: Fugang Duan
18 Feb, 2019
1 commit
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Unlock hw_lock before calling v4l2_m2m_job_finish to avoid deadlock:
v4l2_m2m_job_finish -> v4l2_m2m_try_schedule -> job_ready locks hw_lock
v4l2_m2m_job_finish -> v4l2_m2m_try_run -> device_run locks hw_lockSigned-off-by: Mirela Rabulea
Reviewed-by: Laurentiu Palcu
15 Feb, 2019
5 commits
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Add the speeding grading fuse check to limit the highest speed
of cpu. fuse bits value define as below:
speed_grading bits[1:0] freq(MHz)
0x0 800
0x1 1000
0x2 1300
0x3 1500Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
(cherry picked from commit 0b42acc89cc8752c4a952c116c7905106208e92d) -
Update SCFW APIs to SCFW commit:
004247e14afc ("SCF-341 Fix bug in setting large slice clock divider")Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Reviewed-by: Peng Fan
(cherry picked from commit 89add27a115c3b378d7151299b2919c14a1427ef) -
Update resource ID table to SCFW commit:
004247e14afc ("SCF-341 Fix bug in setting large slice clock divider")Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Reviewed-by: Peng Fan
(cherry picked from commit 8fa8f318eeac939604e2616fd7a6e1fd10d837a0) -
Galcore kernel panic when reading from sysfs during modprobe,
This issue occurs when gc sysfs entries are read while the modprobe
of the galcore module is in progress.Register the GC debugfs attributes in sysfs after the driver data-structures
have been initialized, instead of before.Add defensive sanity checks in all _show() functions used by debugfs
attributes, to check for NULL pointers before dereferencing them.
Return -ENXIO in case of NULL pointers.Signed-off-by: Xianzhong
(cherry picked from commit 3283efbeadbc11cb38146cb7874becfecf27f981) -
GPU hang will happen when run multiple test instances.
link command could be used for context switch often,
it is not reliable to check wait or link command only.need check command address first, then check command.
Signed-off-by: Xianzhong
(cherry picked from commit a7d6f50164039334f371fef1575de7d80d10aa58)
14 Feb, 2019
2 commits
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LSIO_GPIO1 drive the IOEXP_RST signal, its power is off in system
suspend to save power, which introduces reset pulse for expander IO.To avoid unexpected reset, set the PIN to "latch" status before the
GPIO controller is power off during suspend.Signed-off-by: Fugang Duan
(cherry picked from commit: 0c859a75a465d39d10784d95895188bb6f02492e) -
VUY444 is supported by PXP HW but driver miss it. so add it
Signed-off-by: Guoniu.Zhou
(cherry picked from commit 57e9b876954170cd0718eb8af8666573ebb26bb4)
