29 Mar, 2018
1 commit
-
commit 28b2182dad43f6f8fcbd167539a26714fd12bd64 upstream.
Like the Highpoint Rocketraid 642L and cards using a Marvel 88SE9235
controller in general, this RAID card also supports AHCI mode and short
of a custom driver, this is the only way to make it work under Linux.Note that even though the card is called to 644L, it has a product-id
of 0x0645.Cc: stable@vger.kernel.org
BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1534106
Signed-off-by: Hans de Goede
Signed-off-by: Tejun Heo
Acked-by: Bjorn Helgaas
Signed-off-by: Greg Kroah-Hartman
17 Feb, 2018
3 commits
-
commit f919dde0772a894c693a1eeabc77df69d6a9b937 upstream.
Add Intel Cannon Lake PCH-H PCI ID to the list of supported controllers.
Signed-off-by: Mika Westerberg
Signed-off-by: Tejun Heo
Signed-off-by: Greg Kroah-Hartman -
commit 998008b779e424bd7513c434d0ab9c1268459009 upstream.
Add PCI ids for Intel Bay Trail, Cherry Trail and Apollo Lake AHCI
SATA controllers. This commit is a preparation patch for allowing a
different default sata link powermanagement policy for mobile chipsets.Signed-off-by: Hans de Goede
Signed-off-by: Tejun Heo
Signed-off-by: Greg Kroah-Hartman -
commit ca1b4974bd237f2373b0e980b11957aac3499b56 upstream.
Intel uses different SATA PCI ids for the Desktop and Mobile SKUs of their
chipsets. For older models the comment describing which chipset the PCI id
is for, aksi indicates when we're dealing with a mobile SKU. Extend the
comments for recent chipsets to also indicate mobile SKUs.The information this commit adds comes from Intel's chipset datasheets.
This commit is a preparation patch for allowing a different default
sata link powermanagement policy for mobile chipsets.Signed-off-by: Hans de Goede
Signed-off-by: Tejun Heo
Signed-off-by: Greg Kroah-Hartman
03 Oct, 2017
1 commit
-
ahci_pci_reset_controller() calls ahci_reset_controller(), which may
fail, but ignores the result code and always returns success. This
may result in failures like belowahci 0000:02:00.0: version 3.0
ahci 0000:02:00.0: enabling device (0000 -> 0003)
ahci 0000:02:00.0: SSS flag set, parallel bus scan disabled
ahci 0000:02:00.0: controller reset failed (0xffffffff)
ahci 0000:02:00.0: failed to stop engine (-5)
... repeated many times ...
ahci 0000:02:00.0: failed to stop engine (-5)
Unable to handle kernel paging request at virtual address ffff0000093f9018
...
PC is at ahci_stop_engine+0x5c/0xd8 [libahci]
LR is at ahci_deinit_port.constprop.12+0x1c/0xc0 [libahci]
...
[] ahci_stop_engine+0x5c/0xd8 [libahci]
[] ahci_deinit_port.constprop.12+0x1c/0xc0 [libahci]
[] ahci_init_controller+0x80/0x168 [libahci]
[] ahci_pci_init_controller+0x60/0x68 [ahci]
[] ahci_init_one+0x75c/0xd88 [ahci]
[] local_pci_probe+0x3c/0xb8
[] pci_device_probe+0x138/0x170
[] driver_probe_device+0x2dc/0x458
[] __driver_attach+0x114/0x118
[] bus_for_each_dev+0x60/0xa0
[] driver_attach+0x20/0x28
[] bus_add_driver+0x1f0/0x2a8
[] driver_register+0x60/0xf8
[] __pci_register_driver+0x3c/0x48
[] ahci_pci_driver_init+0x1c/0x1000 [ahci]
[] do_one_initcall+0x38/0x120where an obvious hardware level failure results in an unnecessary 15 second
delay and a subsequent crash.So record the result code of ahci_reset_controller() and relay it, rather
than ignoring it.Signed-off-by: Ard Biesheuvel
Signed-off-by: Tejun Heo
06 Sep, 2017
1 commit
-
Intel AHCI controllers that also hide NVMe devices in their bar
can't use MSI interrupts, so disable them.Reported-by: John Loy
Tested-by: John Loy
Signed-off-by: Christoph Hellwig
Fixes: d684a90d38e2 ("ahci: per-port msix support")
Cc: stable@vger.kernel.org # v4.5+
Signed-off-by: Tejun Heo
07 Jul, 2017
1 commit
-
Pull libata updates from Tejun Heo:
- Christoph added support for TCG OPAL self encrypting disks
- Minwoo added support for ATA PASS-THROUGH(32)
- Linus Walleij removed spurious drvdata assignments in some drivers
- Support for a few new device and other fixes
* 'for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: (33 commits)
sd: add support for TCG OPAL self encrypting disks
libata: fix build warning from unused goto label
libata: Support for an ATA PASS-THROUGH(32) command.
ahci: Add Device ID for ASMedia 1061R and 1062R
sata_via: Enable optional hotplug on VT6420
ata: ahci_brcm: Avoid writing to read-only registers
libata: Add the AHCI_HFLAG_NO_WRITE_TO_RO flag
libata: Add the AHCI_HFLAG_YES_ALPM flag
ata: ftide010: fix resource printing
libata: make the function name in comment match the actual function
ata: sata_rcar: make of_device_ids const.
ata: pata_octeon_cf: make of_device_ids const.
libata: Convert bare printks to pr_cont
libahci: wrong comments in ahci_do_softreset()
ata: declare ata_port_info structures as const
ata: Add driver for Faraday Technology FTIDE010
ata: Add DT bindings for the Gemini SATA bridge
ata: Add DT bindings for Faraday Technology FTIDE010
libata: implement SECURITY PROTOCOL IN/OUT
libata: factor out a ata_identify_page_supported helper
...
04 Jul, 2017
1 commit
-
Pull documentation updates from Jonathan Corbet:
"There has been a fair amount of activity in the docs tree this time
around. Highlights include:- Conversion of a bunch of security documentation into RST
- The conversion of the remaining DocBook templates by The Amazing
Mauro Machine. We can now drop the entire DocBook build chain.- The usual collection of fixes and minor updates"
* tag 'docs-4.13' of git://git.lwn.net/linux: (90 commits)
scripts/kernel-doc: handle DECLARE_HASHTABLE
Documentation: atomic_ops.txt is core-api/atomic_ops.rst
Docs: clean up some DocBook loose ends
Make the main documentation title less Geocities
Docs: Use kernel-figure in vidioc-g-selection.rst
Docs: fix table problems in ras.rst
Docs: Fix breakage with Sphinx 1.5 and upper
Docs: Include the Latex "ifthen" package
doc/kokr/howto: Only send regression fixes after -rc1
docs-rst: fix broken links to dynamic-debug-howto in kernel-parameters
doc: Document suitability of IBM Verse for kernel development
Doc: fix a markup error in coding-style.rst
docs: driver-api: i2c: remove some outdated information
Documentation: DMA API: fix a typo in a function name
Docs: Insert missing space to separate link from text
doc/ko_KR/memory-barriers: Update control-dependencies example
Documentation, kbuild: fix typo "minimun" -> "minimum"
docs: Fix some formatting issues in request-key.rst
doc: ReSTify keys-trusted-encrypted.txt
doc: ReSTify keys-request-key.txt
...
27 Jun, 2017
1 commit
-
Adding ASMedia 1061R and 1062R platform device IDs for SATA.
Signed-off-by: Shawn Lin
Signed-off-by: Tejun Heo
16 May, 2017
3 commits
-
The libata documentation is now using ReST. Update references
to it to point to the new place.Signed-off-by: Mauro Carvalho Chehab
Acked-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Tejun Heo -
(Correction in this resend: fixed function name acer_sa5_271_workaround; fixed
the always-true condition in the function; fixed description.)On the Acer Switch Alpha 12 (model number: SA5-271), the internal SSD may not
get detected because the port_map and CAP.nr_ports combination causes the driver
to skip the port that is actually connected to the SSD. More specifically,
either all SATA ports are identified as DUMMY, or all ports get ``link down''
and never get up again.This problem occurs occasionally. When this problem occurs, CAP may hold a
value of 0xC734FF00 or 0xC734FF01 and port_map may hold a value of 0x00 or 0x01.
When this problem does not occur, CAP holds a value of 0xC734FF02 and port_map
may hold a value of 0x07. Overriding the CAP value to 0xC734FF02 and port_map to
0x7 significantly reduces the occurrence of this problem.Link: https://bugzilla.kernel.org/attachment.cgi?id=253091
Signed-off-by: Sui Chen
Tested-by: Damian Ivanov
Cc: stable@vger.kernel.org
Signed-off-by: Tejun Heo -
The libata documentation is now using ReST. Update references
to it to point to the new place.Signed-off-by: Mauro Carvalho Chehab
14 Dec, 2016
1 commit
-
Pull libata updates from Tejun Heo:
- Adam added opt-in ATA command priority support.
- There are machines which hide multiple nvme devices behind an ahci
BAR. Dan Williams proposed a solution to force-switch the mode but
deemed too hackishd. People are gonna discuss the proper way to
handle the situation in nvme standard meetings. For now, detect and
warn about the situation.- Low level driver specific changes.
Christoph Hellwig pipes in about the hidden nvme warning:
"I wish that was the case. We've pretty much agreed that we'll want to
implement it as a virtual PCIe root bridge, similar to Intels other
'innovation' VMD that we work around that way.But Intel management has apparently decided that they don't want to
spend more cycles on this now that Lenovo has an optional BIOS that
doesn't force this broken mode anymore, and no one outside of Intel
has enough information to implement something like this.So for now I guess this warning is it, until Intel reconsideres and
spends resources on fixing up the damage their Chipset people caused"* 'for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
ahci: warn about remapped NVMe devices
ahci-remap.h: add ahci remapping definitions
nvme: move NVMe class code to pci_ids.h
pata: imx: support controller modes up to PIO4
pata: imx: add support of setting timings for PIO modes
pata: imx: set controller PIO mode with .set_piomode callback
pata: imx: sort headers out
ata: set ncq_prio_enabled iff device has support
ata: ATA Command Priority Disabled By Default
ata: Enabling ATA Command Priorities
block: Add iocontext priority to request
ahci: qoriq: added ls1046a platform support
06 Dec, 2016
1 commit
-
Some Intel ahci implementations have a completely broken remapping mode
where they hide one or more NVMe devices behind the bar of an AHCI device.Intel refuses to let the OS reprogram the BIOS to switch out of this
mode at runtime, and so far we're not come up with another good way
to undo the mess that the Chipset people created. So for now the only
thing we can do is to alert users about this situation and switch to the
faster and much saner so called "AHCI" mode insted of the RAID mode in
the BIOS so that the BIOS does not hide the NVMe devices from us.The sitation is even worse as at least one vendor (thanks a lot Lenovo..)
has started hardcoding their BIOS into the "RAID" mode even for laptops
that don't use AHCI _at all_ and just have a single NVMe device. For now
there is an unspported Linux-only BIOS that undoes this braindamage,
but we'll have to see if things are getting better or worse from here.Based on an earlier patch from Dan Williams .
Signed-off-by: Christoph Hellwig
Signed-off-by: Tejun Heo
22 Nov, 2016
1 commit
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Don't try to guess what the errors from pci_irq_alloc_vectors mean, as
that's too fragile. Instead always try allocating a single vector
when multi-MSI mode fails. This makes various intel Desktop and
Laptop CPUs use MSI again.Signed-off-by: Christoph Hellwig
Reported-by: Michael Marley
Tested-by: Michael Marley
Fixes: 0b9e2988ab22 ("ahci: use pci_alloc_irq_vectors")
Signed-off-by: Tejun Heo
25 Oct, 2016
1 commit
-
We need to make sure hpriv->irq is set properly if we don't use per-port
vectors, so switch from blindly assigning pdev->irq to using
pci_irq_vector, which handles all interrupt types correctly.Signed-off-by: Christoph Hellwig
Reported-by: Robert Richter
Tested-by: Robert Richter
Tested-by: David Daney
Fixes: 0b9e2988ab22 ("ahci: use pci_alloc_irq_vectors")
Signed-off-by: Tejun Heo
21 Oct, 2016
1 commit
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commit 17a51f12 ("ahci: only try to use multi-MSI mode if there is more
than 1 port") lead to a case where nvec isn't initialized before it's
used. Fix this by moving the check into the n_ports conditional.Reported-and-reviewed-by Colin Ian King
Signed-off-by: Christoph Hellwig
Signed-off-by: Tejun Heo
20 Oct, 2016
1 commit
-
We should only try to allocate multiple MSI or MSI-X vectors if the device
actually has multiple ports. Otherwise pci_alloc_irq_vectors will return
a single vector due to n_ports = 1, in which case we shouldn't set the
AHCI_HFLAG_MULTI_MSI flag.Signed-off-by: Christoph Hellwig
Fixes: 0b9e2988 ("ahci: use pci_alloc_irq_vectors")
Reported-by: Emmanuel Benisty
Tested-by: Emmanuel Benisty
Signed-off-by: Tejun Heo
07 Sep, 2016
1 commit
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Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors.
The big advantage over the old code is that we can use the same API for
MSI and MSI-X, and that we don't need to store the MSI-X vector mapping
in driver-private data structures.This first conversion keeps the probe order as-is: MSI-X multi vector,
MSI multi vector, MSI single vector, MSI-X single vector and last a
single least legacy interrupt line. There is one small change of
behavior: we now check the "MSI Revert to Single Message" flag for
MSI-X in addition to MSI.Because the API to find the Linux IRQ number for a MSI/MSI-X vector
is PCI specific, but libahaci is bus-agnostic I had to a
get_irq_vector function pointer to struct ahci_host_priv. The
alternative would be to move the multi-vector case of ahci_host_activate
to ahci.c and just call ata_host_activate directly from the others
users of ahci_host_activate.Signed-off-by: Christoph Hellwig
Signed-off-by: Tejun Heo
27 May, 2016
1 commit
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The IS_ENABLED() macro checks if a Kconfig symbol has been enabled either
built-in or as a module, use that macro instead of open coding the same.Signed-off-by: Javier Martinez Canillas
Signed-off-by: Tejun Heo
12 Mar, 2016
2 commits
-
These PCI device IDs have been removed from the Intel Lewisburg design
specification. They are no longer needed.Signed-off-by: Scott Lawson
Signed-off-by: Tejun Heo
01 Mar, 2016
1 commit
-
Due to Errata in ThunderX, HOST_IRQ_STAT should be
cleared before leaving the interrupt handler.
The patch attempts to satisfy the need.Changes from V2:
- removed newfile
- code is now under CONFIG_ARM64Changes from V1:
- Rebased on top of libata/for-4.6
- Moved ThunderX intr handler to new filetj: Minor adjustments to comments.
Signed-off-by: Tirumalesh Chalamarla
Signed-off-by: Tejun Heo
19 Feb, 2016
3 commits
-
This patch adds runtime PM support for the AHCI host controller driver so
that the host controller is powered down when all SATA ports are runtime
suspended. Powering down the AHCI host controller can reduce power
consumption and possibly allow the CPU to enter lower power idle states
(S0ix) during runtime.Runtime PM is blocked by default and needs to be unblocked from userspace
as needed (via power/* sysfs nodes).Signed-off-by: Mika Westerberg
Signed-off-by: Tejun Heo -
In order to add support for runtime PM to the ahci driver we first need to
convert the driver to use modern non-legacy system suspend hooks. There
should be no functional changes.tj: Updated .driver.pm init for older compilers as suggested by Andy
and Chrsitoph.Signed-off-by: Mika Westerberg
Cc: Andy Shevchenko
Cc: Christoph Hellwig
Signed-off-by: Tejun Heo -
This patch complements the list of device IDs previously
added for lewisburg sata.Signed-off-by: Alexandra Yates
Signed-off-by: Tejun Heo
Cc: stable@vger.kernel.org
11 Feb, 2016
1 commit
-
Adding Intel codename DNV platform device IDs for SATA.
Signed-off-by: Alexandra Yates
Signed-off-by: Tejun Heo
Cc: stable@vger.kernel.org
17 Nov, 2015
3 commits
-
Some AHCI controllers support per-port MSI-X vectors. At the same time
the Linux AHCI driver needs to support one-off architectures that
implement a single MSI-X vector for all ports. The heuristic for
enabling AHCI ports becomes, in order of preference:1/ per-port multi-MSI-X
2/ per-port multi-MSI
3/ single MSI
4/ single MSI-X
5/ legacy INTX
This all depends on AHCI implementations with potentially broken MSI-X
requesting less vectors than the number of ports. If this assumption is
violated we will need to start explicitly white-listing AHCI-MSIX
implementations.Reported-by: Ricardo Neri
[ricardo: fix struct msix_entry handling]
Reported-by: kernel test robot
Signed-off-by: Dan Williams
Signed-off-by: Tejun Heo -
This change was to preserve the ascending order of device IDs.
There was an exception with the first two Lewisburg device IDs to
keep all device IDs of the same kind grouped by code name.Signed-off-by: Alexandra Yates
signed-off-by: Tejun Heo -
This patch adds missing AHCI RAID SATA Device IDs for the Intel Sunrise
Point PCH.Signed-off-by: Nanda Kishore Chinna
Signed-off-by: Charles Rose
Signed-off-by: Tejun Heo
04 Nov, 2015
1 commit
-
Adding Intel codename Lewisburg platform device IDs for SATA.
Signed-off-by: Alexandra Yates
Signed-off-by: Tejun Heo
31 Oct, 2015
1 commit
-
Add device id for Marvell 88se91a2
Signed-off-by: Johannes Thumshirn
Signed-off-by: Tejun Heo
25 Aug, 2015
1 commit
-
On multi-function JMicron SATA/PATA/AHCI devices, the PATA controller at
function 1 doesn't work if it is powered on before the SATA controller at
function 0. The result is that PATA doesn't work after resume, and we
print messages like this:pata_jmicron 0000:02:00.1: Refused to change power state, currently in D3
irq 17: nobody cared (try booting with the "irqpoll" option)Async resume was introduced in v3.15 by 76569faa62c4 ("PM / sleep:
Asynchronous threads for resume_noirq"). Prior to that, we powered on
the functions in order, so this problem shouldn't happen.e6b7e41cdd8c ("ata: Disabling the async PM for JMicron chip 363/361")
solved the problem for JMicron 361 and 363 devices. With async suspend
disabled, we always power on function 0 before function 1.Barto then reported the same problem with a JMicron 368 (see comment #57 in
the bugzilla).Rather than extending the blacklist piecemeal, disable async suspend for
all JMicron multi-function SATA/PATA/AHCI devices.This quirk could stay in the ahci and pata_jmicron drivers, but it's likely
the problem will occur even if pata_jmicron isn't loaded until after the
suspend/resume. Making it a PCI quirk ensures that we'll preserve the
power-on order even if the drivers aren't loaded.[bhelgaas: changelog, limit to multi-function, limit to IDE/ATA]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=81551
Reported-and-tested-by: Barto
Signed-off-by: Zhang Rui
Signed-off-by: Bjorn Helgaas
CC: stable@vger.kernel.org # v3.15+
26 Jun, 2015
1 commit
-
Pull libata updates from Tejun Heo:
- a number of libata core changes to better support NCQ TRIM.
- ahci now supports MSI-X in single IRQ mode to support a new
controller which doesn't implement MSI or INTX.- ahci now supports edge-triggered IRQ mode to support a new controller
which for some odd reason did edge-triggered IRQ.- the usual controller support additions and changes.
* 'for-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: (27 commits)
libata: Do not blacklist Micron M500DC
ata: ahci_mvebu: add suspend/resume support
ahci, msix: Fix build error for !PCI_MSI
ahci: Add support for Cavium's ThunderX host controller
ahci: Add generic MSI-X support for single interrupts to SATA PCI driver
libata: finally use __initconst in ata_parse_force_one()
drivers: ata: add support for Ceva sata host controller
devicetree:bindings: add devicetree bindings for ceva ahci
ahci: added support for Freescale AHCI sata
ahci: Store irq number in struct ahci_host_priv
ahci: Move interrupt enablement code to a separate function
Doc: libata: Fix spelling typo found in libata.xml
ata:sata_nv - Change 1 to true for bool type variable.
ata: add Broadcom AHCI SATA3 driver for STB chips
Documentation: devicetree: add Broadcom SATA binding
libata: Fix regression when the NCQ Send and Receive log page is absent
ata: hpt366: fix constant cast warning
ata: ahci_xgene: potential NULL dereference in probe
ata: ahci_xgene: Add AHCI Support for 2nd HW version of APM X-Gene SoC AHCI SATA Host controller.
libahci: Add support to handle HOST_IRQ_STAT as edge trigger latch.
...
18 Jun, 2015
1 commit
-
It turned out the irq vector of the msix can be obtained from struct
msix_entry. This makes the lookup function for msi_desc obsolete.This fixes a build error if PCI_MSI is unset:
drivers/ata/ahci.c: In function ‘msix_get_desc’:
drivers/ata/ahci.c:1210:2: error: ‘struct pci_dev’ has no member named ‘msi_list’Catched by Fengguang's build bot.
Reported-by: kbuild test robot
Signed-off-by: Robert Richter
Signed-off-by: Tejun Heo
17 Jun, 2015
2 commits
-
This patch adds support for Cavium's ThunderX host controller. The
controller resides on the SoC and is a AHCI compatible SATA controller
with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31.
There can exists multiple SATA controllers on the SoC.The controller depends on MSI-X support since the PCI ECAM controller
on the SoC does not implement MSI nor lagacy intx interrupt support.
Thus, during device initialization, if MSI fails MSI-X will be used to
enable the device's interrupts.The controller uses non-standard BAR0 for its register range. The
already existing device lookup (vendor and device id) that is already
implemented for other host controllers is used to change the PCI BAR.Signed-off-by: Robert Richter
Signed-off-by: Tejun Heo -
This patch adds generic MSI-X support for single interrupts to the
SATA PCI driver. MSI-X support is needed for host controller that only
have MSI-X support implemented, but no MSI or intx. This patch only
adds support for single interrupts, multiple per-port MSI-X interrupts
are not yet implemented.The new implementation still initializes MSIs first. Only if that
fails, the code tries to enable MSI-X. If that fails too, setup is
continued with intx interrupts.To not break other chips by this generic code change, there are the
following precautions:* Interrupt ranges are not enabled at all.
* Only single interrupt mode is enabled for msix cap devices. Thus,
only one interrupt will be setup.* During the discussion with Tejun we agreed to change the init
sequence from msix-msi-intx to msi-msix-intx. Thus, if a device
offers msi and init does not fail, the msix init code will not be
executed. This is equivalent to current code.With this, the code only setups single mode msix as a last resort if
msi fails. No interrupt range is enabled at all. Only one interrupt
will be enabled.tj: comment edits.
Changes of the patch series:
v5:
* updated patch subject that the patch only implements single IRQ
* moved Cavium specific code to a separate patch
* detect Cavium ThunderX device with PCI_CLASS_STORAGE_SATA_AHCI
instead of vendor/dev id
* added more comments to the code
* enable single msix support for all kind of devices (removing strict
check)
* rebased onto update libata/for-4.2 with patch 1, 2 appliedv4:
* removed implementation of ahci_init_intx()
* improved patch descriptions
* rebased onto libata/for-4.2v3:
* store irq number in struct ahci_host_priv
* change initialization order from msix-msi-intx to msi-msix-intx
* improve comments in ahci_init_msix()
* improve error message in ahci_init_msix()
* do not enable MSI-X if MSI is actively disabled for the devicev2:
* determine irq vector from pci_dev->msi_listBased on a patch from Sunil Goutham .
Signed-off-by: Robert Richter
Signed-off-by: Tejun Heo
03 Jun, 2015
2 commits
-
Currently, ahci supports only msi and intx. To also support msix the
handling of the irq number need to be changed. The irq number for msix
devices is taken from msi_list instead of pci_dev. Thus, the irq
number of a device needs to be stored in struct ahci_host_priv now.
This allows the host controller to be activated in a generic way.This change is only intended for ahci drivers. For that reason the irq
number is stored in struct ahci_host_priv used only by ahci drivers.
Thus, the ABI changes only for ahci_host_activate(), but existing ata
drivers (about 50) are unaffected and keep unchanged. All users of
ahci_host_activate() have been updated.While touching drivers/ata/libahci.c, doing a small code cleanup in
ahci_port_start().Signed-off-by: Robert Richter
Signed-off-by: Tejun Heo -
This patch refactors ahci_init_interrupts() and moves msi code to a
separate function. Need the split since we add msix initialization in
a later patch. The initialization for msix will be done after msi but
before intx.Signed-off-by: Robert Richter
Signed-off-by: Tejun Heo
10 May, 2015
1 commit
-
Avoton AHCI occasionally sees drive probe timeouts at driver load time.
When this happens SCR_STATUS indicates device detected, but no D2H FIS
reception. Reset the internal link state machines by bouncing
port-enable in the PCS register when this occurs.Cc:
Signed-off-by: Dan Williams
Signed-off-by: Tejun Heo
