14 Sep, 2022
1 commit
17 Aug, 2022
1 commit
14 Jun, 2022
1 commit
13 Jun, 2022
1 commit
26 Oct, 2021
1 commit
21 Jul, 2021
1 commit
19 Jul, 2021
1 commit
06 Mar, 2021
1 commit
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After reduce the panel RM67191's pixel clock from 132MHz to
121MHz by 'commit 4193a9c3254b ("MLK-3056-2 drm/panel: rm67191:
change clock rate to 121MHz for default mod")', the disp_apb
clock rate needs to be configured properly to avoid the issue
described in LF-33886 ticket with currrent disp_apb clock config
like below:sys1_pll_out 5 5 0 800000000 0 0 50000
sys1_pll_800m 5 5 0 800000000 0 0 50000
disp_apb 1 1 0 133333334 0 0 50000
disp_apb_root_clk 2 2 0 133333334 0 0 50000And configure disp_apb rate to 25MHz like below can solve this
issue:sys1_pll_out 5 5 0 800000000 0 0 50000
sys1_pll_800m 5 5 0 800000000 0 0 50000
disp_apb 1 1 0 25000000 0 0 50000
disp_apb_root_clk 2 2 0 25000000 0 0 50000Signed-off-by: Fancy Fang
Reviewed-by: Robby Cai
Acked-by: Jason Liu
04 Mar, 2021
1 commit
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On 8DXL, the LCDIF IRQ number is different from 8QXP, so fix it in the
specific 8dxl dts file.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu
Acked-by: Jason Liu
23 Feb, 2021
1 commit
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When M4 boots from flexspi, linux should not use that, otherwise
M4 will hang.Reviewed-by: Richard Zhu
Signed-off-by: Peng Fan
(cherry picked from commit 1f49d90ebaf77492bcb2e9f8a8e5a8d4d7aee58a)
Acked-by: Jason Liu
03 Feb, 2021
1 commit
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Add the missing pmu node and also fix the issue with kvm that it
requires pmu node to be present.Signed-off-by: Li Yang
Acked-by: Diana Craciun
30 Jan, 2021
1 commit
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Clocks are always on when DSP PD is on. Use dummy clocks
for minimal code impact for now.This is similar with the approach on i.MX8QM.
Signed-off-by: Daniel Baluta
26 Jan, 2021
1 commit
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Fix i2c address for second and third ak4458 dac on Audio
Board 2.0Signed-off-by: Hongting Dong
Reviewed-by: Adrian Alonso
25 Jan, 2021
2 commits
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This reverts commit d367e7d3351edc526133e4bd258dac2dd0b4ef4f.
As designed, the default dtb imx8mq-evk can only support one
display: DCSS + native HDMI, and dtb imx8mq-evk-dual-display
is dedicated for multiple dislay.And current multiple displays is implemented by two different
DRM devices with two DRI cards generated. But Weston UI cannot
make sure to choose DCSS for UI display device, so revert this
patch to solve this kind of problem.Signed-off-by: Fancy Fang
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Add phy tuning result for USB certification, mainly for pass
eye pattern test, details please check its dt binding doc:
Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txtReviewed-by: Haibo Chen
Reviewed-by: Peter Chen
Signed-off-by: Li Jun
22 Jan, 2021
1 commit
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With mailbox driver support i.MX8 SCU MU channel, we could
use it to avoid trigger interrupts for each TR/RR registers
in one MU, instead, only one RX interrupt for a recv and
one TX interrupt for a send.Signed-off-by: Nitin Garg
Reviewed-by: Dong Aisheng
20 Jan, 2021
1 commit
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add the gpio-scu node and enable on-board phy for
enet0 by default.remove "enable-active-high" property from mii_select node to
use the enet module.Signed-off-by: Shenwei Wang
13 Jan, 2021
5 commits
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simple-card uses 'Headphones' instead of 'Headphone Jack'
for gpio pin name,Without the current patch we get this error:
asoc-simple-card sof-sound-wm8960: ASoC: DAPM unknown pin HeadphonesReviewed-by: Viorel Suman
Signed-off-by: Daniel Baluta -
There is no mic-det-gpio so remove it. Fix hp-det-gpio flags
to match non-sof usecase.Reviewed-by: Viorel Suman
Signed-off-by: Daniel Baluta -
According to 8MPLUSS-BB schematic:
- HP_MIC1P -> LINPUT3 / JD2
- X -> LINPUT2
- HP_MIC1N -> LINPUT1
- HP_JD -> RINPUT3 / JD3
- X -> RINPUT2
- X -> RINPUT1Fix the routing map according to schematic.
Reviewed-by: Viorel Suman
Signed-off-by: Daniel Baluta -
Add MICB -> Mic Jack connection in order to power up Microphone.
Reviewed-by: Viorel Suman
Signed-off-by: Daniel Baluta -
Property name for routing used by simple card is 'routing' not
'audio-routing'.Reviewed-by: Viorel Suman
Signed-off-by: Daniel Baluta
12 Jan, 2021
1 commit
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The fourth number in interrupt-map represents different interrupt
sources so that should be set to a different value.Reviewed-by: Peng Fan
Signed-off-by: Alice Guo
08 Jan, 2021
1 commit
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Add hdcp-config property for imx8 hdmi tx hdcp.
hdcp-config default configurate to 3.hdcp-config = /* For HDCP1.4 only */
hdcp-config = /* For HDCP2.2 only */
hdcp-config = /* For both HDCP2.2 and HDCP1.4 */Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
07 Jan, 2021
1 commit
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This patch adds the V2X subsystem in which the different
MUs to access the V2X are listed. Without this patch the DXL
fails to enter KS1 as V2X resource is left ON and suspend
power is very high.Signed-off-by: Stéphane Dion
Signed-off-by: Nitin Garg
Reviewed-by: Dong Aisheng
05 Jan, 2021
5 commits
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enable sdma1 as i.mx8mm-evk-rpmsg.dts.
Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang -
enable sdma1 as i.mx8mm-evk-rpmsg.dts.
Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang -
enable sdma1 as i.mx8mm-evk-rpmsg.dts.
Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang -
enable sdma1 as i.mx8mm-evk-rpmsg.dts.
Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang -
Enable sdma1 since Yocto use sdma1 as udev rule to trigger firmware
loader, actually, m4 do not need to disable sdma1 because it's standlone
demo which means don't care kernel bootup. Enable it in rpmsg dtb to
ensure sdma firmware load successfully as the default dtb.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang
04 Jan, 2021
1 commit
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This is the 5.10.4 stable release
* tag 'v5.10.4': (717 commits)
Linux 5.10.4
x86/CPU/AMD: Save AMD NodeId as cpu_die_id
drm/edid: fix objtool warning in drm_cvt_modes()
...Signed-off-by: Jason Liu
Conflicts:
drivers/gpu/drm/imx/dcss/dcss-plane.c
drivers/media/i2c/ov5640.c
30 Dec, 2020
9 commits
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commit f43cadef2df260101497a6aace05e24201f00202 upstream.
FW has to configure devices' StreamIDs so that SMMU is able to lookup
context and do proper translation later on. For Armada 7040 & 8040 and
publicly available FW, most of the devices are configured properly,
but some like ap_sdhci0, PCIe, NIC still remain unassigned which
results in SMMU faults about unmatched StreamID (assuming
ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y).Since there is dependency on custom FW let SMMU be disabled by default.
People who still willing to use SMMU need to enable manually and
use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line)
with extra caution.Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support")
Cc: # 5.9+
Signed-off-by: Tomasz Nowicki
Signed-off-by: Gregory CLEMENT
Signed-off-by: Greg Kroah-Hartman -
commit 50301e8815c681bc5de8ca7050c4b426923d4e19 upstream.
DSS is IO coherent on AM65, so we should mark it as such with
'dma-coherent' property in the DT file.Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node")
Signed-off-by: Tomi Valkeinen
Signed-off-by: Nishanth Menon
Acked-by: Nikhil Devshatwar
Cc: stable@vger.kernel.org # v5.8+
Link: https://lore.kernel.org/r/20201102134650.55321-1-tomi.valkeinen@ti.com
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit 9e454e37dc7c0ee9e108d70b983e7a71332aedff ]
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
egisters. On similar boards with the same PHY this fixes an issue where
Ethernet link would not come up when using ip link set down/up.Fixes: 2cd2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial device-tree")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
Signed-off-by: Kevin Hilman
Link: https://lore.kernel.org/r/46298e66572784c44f873f1b71cc4ab3d8fc5aa6.1607363522.git.stefan@agner.ch
Signed-off-by: Sasha Levin -
[ Upstream commit 3d07c3b3a886fefd583c1b485b5e4e3c4e2da493 ]
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
registers. On similar boards with the same PHY this fixes an issue where
Ethernet link would not come up when using ip link set down/up.Fixes: ed5e8f689154 ("arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
Signed-off-by: Kevin Hilman
Link: https://lore.kernel.org/r/12506964ca5d5f936579a280ad0a7e7f9a0a2d4c.1607363522.git.stefan@agner.ch
Signed-off-by: Sasha Levin -
[ Upstream commit c183c406c4321002fe85b345b51bc1a3a04b6d33 ]
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
registers. This fixes an issue seen on ODROID-C2 where the Ethernet
link doesn't come up when using ip link set down/up:
[ 6630.714855] meson8b-dwmac c9410000.ethernet eth0: Link is Down
[ 6630.785775] meson8b-dwmac c9410000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=36)
[ 6630.893071] meson8b-dwmac c9410000.ethernet: Failed to reset the dma
[ 6630.893800] meson8b-dwmac c9410000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 6630.902835] meson8b-dwmac c9410000.ethernet eth0: stmmac_open: Hw setup failedFixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
Signed-off-by: Kevin Hilman
Link: https://lore.kernel.org/r/4a322c198b86e4c8b3dda015560a683babea4d63.1607363522.git.stefan@agner.ch
Signed-off-by: Sasha Levin -
[ Upstream commit 1c7412530d5d0e0a0b27f1642f5c13c8b9f36f05 ]
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
registers. This fixes an issue where the Ethernet link doesn't come up
when using ip link set down/up:
[ 29.360965] meson8b-dwmac ff3f0000.ethernet eth0: Link is Down
[ 34.569012] meson8b-dwmac ff3f0000.ethernet eth0: PHY [0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31)
[ 34.676732] meson8b-dwmac ff3f0000.ethernet: Failed to reset the dma
[ 34.678874] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 34.687850] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_open: Hw setup failedFixes: 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
Signed-off-by: Kevin Hilman
Link: https://lore.kernel.org/r/df3f5c4fc6e43c55429fd3662a636036a21eed49.1607363522.git.stefan@agner.ch
Signed-off-by: Sasha Levin -
[ Upstream commit 94dad6bed3c86c00050bf7c2b2ad6b630facae31 ]
For UARTs, the local pull-ups should be on the RX pin, not the TX pin.
UARTs transmit active-low, so a disconnected RX pin should be pulled
high instead of left floating to prevent noise being interpreted as
transmissions.This gets rid of bogus sysrq events when the UART console is not
connected.Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs")
Signed-off-by: Chen-Yu Tsai
Link: https://lore.kernel.org/r/20201204064805.6480-1-wens@kernel.org
Signed-off-by: Heiko Stuebner
Signed-off-by: Sasha Levin -
[ Upstream commit b6a1c8a1eaa73b1e2ae251399308e9445d74cef7 ]
The freqency 1512000000 should be 1500000000.
Signed-off-by: Dongjin Kim
Fixes: 3d9e76483049 ("arm64: dts: meson-sm1-sei610: enable DVFS")
Reviewed-by: Neil Armstrong
Signed-off-by: Kevin Hilman
Link: https://lore.kernel.org/r/20201130060320.GA30098@anyang-linuxfactory-or-kr
Signed-off-by: Sasha Levin -
[ Upstream commit b6c605e00ce8910d7ec3d9a54725d78b14db49b9 ]
The max frequency for the w25q32 (VIM v1.2) and w25q128 (VIM v1.4) spifc
chip should be 104Mhz not 30MHz.Fixes: b8b74dda3908 ("ARM64: dts: meson-gxm: Add support for Khadas VIM2")
Signed-off-by: Artem Lapkin
Reviewed-by: Neil Armstrong
Signed-off-by: Kevin Hilman
Link: https://lore.kernel.org/r/20201125024001.19036-1-christianshewitt@gmail.com
Signed-off-by: Sasha Levin
