14 Jan, 2020
4 commits
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Add support for eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
Reviewed-by: Andy Shevchenko
Signed-off-by: Kishon Vijay Abraham I -
Add a YAML schema to use the host controller driver with the
eMMC PHY on Intel's Lightning Mountain SoC.Signed-off-by: Ramuthevar Vadivel Murugan
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I -
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig), two divider clocks and supports
resets for each of the lanes.[jsarha@ti.com: Add support for Torrent(10G) SERDES wrapper]
Signed-off-by: Jyri Sarha
Signed-off-by: Kishon Vijay Abraham I -
Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a
PHY but a wrapper used to configure some of the input signals to the
SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.Signed-off-by: Kishon Vijay Abraham I
[jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)
SERDES]
Signed-off-by: Jyri Sarha
Reviewed-by: Rob Herring
08 Jan, 2020
36 commits
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commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"),
incorrectly used parent device pointer to get driver data. Fix it here.Signed-off-by: Kishon Vijay Abraham I
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Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
as specified in "Common Module Clock Configurations" of the Cadence
Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz
since the only user of Cadence Sierra SERDES, TI J721E SoC provides
input clock frequency of 100MHz. For other frequencies,
cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured
based on the "Common Module Clock Configurations".Signed-off-by: Kishon Vijay Abraham I
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Sierra SERDES IP supports upto 16 lanes (though not all of it
will be enabled in a platform). Allow Sierra driver to support a
maximum of upto 16 lanes.Signed-off-by: Kishon Vijay Abraham I
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Check for PLL lock during PHY power on.
Signed-off-by: Kishon Vijay Abraham I
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A link may have multiple lanes each with a separate reset. Get
reset control "array" in order to reset all the lanes associated
with the link.Signed-off-by: Kishon Vijay Abraham I
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The existing configuration done in Cadence Sierra driver is only for
reference and is not used in any platforms. Remove them and configure
both lane cdb and common cdb registers to be used with external
SSC configuration. This is validated in TI J721E platform.Signed-off-by: Anil Varughese
Signed-off-by: Kishon Vijay Abraham I -
No functional change. Modify register offset macro names to be in sync with
Sierra user guide.Signed-off-by: Kishon Vijay Abraham I
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Instead of invoking cdns_sierra_phy_init() from probe, add it in
phy_ops so that it's initialized when the PHY consumer invokes
phy_init()Signed-off-by: Kishon Vijay Abraham I
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SERDES_16G in TI's J721E SoC uses Cadence Sierra PHY. Add
support to use Cadence Sierra driver in J721E SoC.Signed-off-by: Kishon Vijay Abraham I
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Use "regmap" for read and write to Sierra registers. This is in
perparation for adding SERDES_16G support present in TI's J721E
SoC.Signed-off-by: Kishon Vijay Abraham I
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Certain platforms like TI J721E using Cadence Sierra Serdes
doesn't provide explicit phy_clk and reset (APB reset) control.
Make them optional here.Signed-off-by: Kishon Vijay Abraham I
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Add DT binding documentation for Sierra PHY IP used in TI's J721E
SoC.Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring -
Add support for 7211 USB wake. Disable all possible 7211 USB logic
for S2/S5 if USB wake is not enabled.On the 7211, the XHCI wake signal was not connected properly and
only goes to the USB1_USB1_CTRL_TP_DIAG1 diagonstic register.
The workaround is to have VPU code running that polls for the
proper bit in the DIAG register and to wake the system when
the bit is asserted.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
This is a result of the USB 2.0 clocks not being disabled/enabled
during suspend/resume on XHCI only systems.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The BDC "Read Transaction Size" needs to be changed from 1024
bytes to 256 bytes to prevent occasional transaction failures.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
When there is no device connected and FSM is enabled, the XHCI puts
the PHY into suspend mode. When the PHY is put into suspend mode
the USB LDO powers down the PHY. This causes the MDIO to be
inaccessible and its registers reset to default. The fix is to
disable FSM.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Handle defer on clk_get because the new SCMI clock driver comes
up after this driver.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The 7211b0 has added the STB XHCI Synopsys controller and it
will be used instead of the RPi based DWC USB controller. The new
Synopsys XHCI controller core is the same one that is used on the
7216, but because of the way the STB USB PHY is used on both the A0
and B0, some of the PHY control is different.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The 7216 has the new USB XHCI controller from Synopsys. While
this new controller and the PHY are similar to the STB versions,
the major differences are:- Many of the registers and fields in the CTRL block have been
removed or changed.
- A new set of Synopsys control registers, BCHP_USB_XHCI_GBL, were
added.
- MDIO functionality has been replaced with direct access registers
in the BCHP_USB_XHCI_GBL block.
- Power up PHY defaults that had to be changed by MDIO in previous
chips will now power up with the correct defaults.A new init module was created for this new Synopsys USB controller.
A new compatible string was added and the driver will dispatch
into one of two init modules based on it. A "reg-names" field was
added so the driver can more easily get optional registers.
A DT bindings document was also added for this driver.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Add support for bcm7216 and bcm7211
Signed-off-by: Al Cooper
Reviewed-by: Rob Herring
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The driver is being restructured in preparation for adding support
for the new Synopsys USB conroller on the 7216. Since all the bugs
and work-arounds in previous STB chips are supposed to be fixed,
most of the code in phy-brcm-usb-init.c is not needed. Instead of
adding more complexity to the already complicated phy-brcm-usb-init.c
module, the driver will be restructured to use a vector table to
dispatch into different C modules for the different controllers.There was also some general cleanup done including some ipp setup
code that was incorrect.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Add the ability to handle USB wake events from USB devices when
in S2 mode. Typically there is some additional configuration
needed to tell the USB device to generate the wake event when
suspended but this varies with the different USB device classes.
For example, on USB Ethernet dongles, ethtool should be used to
enable the magic packet wake functionality in the dongle.
NOTE: This requires that the "power/wakeup" sysfs entry for
the USB device generating the wakeup be set to "enabled".This functionality requires a special hardware sideband path that
will trigger the AON_PM_L2 interrupt needed to wake the system from
S2 even though the USB host controllers are in IDDQ (low power state)
and most USB related clocks are shut off. For the sideband signaling
to work we need to leave the usbx_freerun clock running, but this
clock consumes very little power by design. There's a bug in the
XHCI wake hardware so only EHCI/OHCI wake is currently supported.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Currently the Phy driver will put the USB phys into the max
power saving mode (IDDQ) when there is no corresponding XHCI, EHCI
or OHCI client (through rmmod, unbind or if the driver is not
builtin). This change will also put the Phys into IDDQ mode
on suspend so that S2 will get the additional power savings.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
The BRCM USB Phy, ohci, ehci and xhci drivers all use the USB clocks
but not all drivers use the clk_prepare_enable/clk_disable_unprepare
versions to enable/disable the clocks. This change gets all drivers
using the prepare version.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
When the EHCI controller received a 512 byte USB packet that
had to be broken into 2 256 byte bursts across the SCB bus AND
there was a following 512 byte USB packet, the second burst of
data from the first packet was sometimes being lost. If the
burst size was changed to 128 bytes via the EBR_SCB_SIZE field
in the USB_CTRL_EBRIDGE register we'd see the 4th 128 byte burst
of the first packet being lost. This problem became much worse
if other threads were running that accessed memory, like a memcpy
test. Setting the EBR_SCB_SIZE to 512, which prevents breaking
the EHCI USB packet (max size of 512 bytes) into bursts, fixed
the problem.Signed-off-by: Al Cooper
Reviewed-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
then deassert it, so add the QPHY_SW_RESET register which does this.Signed-off-by: Vinod Koul
Reviewed-by: Manu Gautam
Reviewed-by: Can Guo
Signed-off-by: Kishon Vijay Abraham I -
SM8150 QMPY phy for UFS and onwards the PHY_SW_RESET is present in PHY's
PCS register so we should not mark no_pcs_sw_reset for sm8150 and
onwardsSigned-off-by: Vinod Koul
Reviewed-by: Manu Gautam
Reviewed-by: Can Guo
Signed-off-by: Kishon Vijay Abraham I -
We already write to QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init()
before invoking qcom_qmp_phy_configure() so remove the duplicate write.Signed-off-by: Vinod Koul
Reviewed-by: Manu Gautam
Signed-off-by: Kishon Vijay Abraham I -
We already define register offsets so use them in register layout.
Signed-off-by: Vinod Koul
Reviewed-by: Manu Gautam
Reviewed-by: Can Guo
Signed-off-by: Kishon Vijay Abraham I -
7216 is a 16nm process chip with a slightly different version of the PHY
SerdDeS/AFE that requires a specific tuning sequence. Key on the
compatible string to perform that initialization.Signed-off-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I -
Define "brcm,bcm7216-sata-phy" as a new compatible string for the
Broadcom SATA3 PHY.Signed-off-by: Florian Fainelli
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I -
During review it came to light that exposing the pll clock outside is
not the right approach and struct phy_configure_opts_mipi_dphy exists
just for that reason to transfer parameters to the phy.So drop the exposed clock and rely on the phy configure options
to bring in the correct rate. That way we can also just drop the
open coded timing struct and default values function.Fixes: b7535a3bc0ba ("phy/rockchip: Add support for Innosilicon MIPI/LVDS/TTL PHY")
Signed-off-by: Heiko Stuebner
Signed-off-by: Kishon Vijay Abraham I -
Further review of the dsi components for the px30 revealed that the
phy shouldn't expose the pll as clock but instead handle settings
via phy parameters.As the phy binding is new and not used anywhere yet, just drop them
so they don't get used.Fixes: 3817c7961179 ("dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy")
Signed-off-by: Heiko Stuebner
Signed-off-by: Kishon Vijay Abraham I -
Fixes coccicheck warning:
drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c:389:2-3: Unneeded semicolon
Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY")
Reported-by: Hulk Robot
Signed-off-by: Ma Feng
Signed-off-by: Kishon Vijay Abraham I -
Clang warns:
../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:83:4: warning:
misleading indentation; statement is not part of the previous 'if'
[-Wmisleading-indentation]
usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
^
../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:80:3: note: previous
statement is here
if (readl_relaxed(addr) & mask)
^
1 warning generated.This warning occurs because there is a space after the tab on this line.
Remove it so that the indentation is consistent with the Linux kernel
coding style and clang no longer warns.Fixes: 1de990d8a169 ("phy: qcom: Add driver for QCOM APQ8064 SATA PHY")
Link: https://github.com/ClangBuiltLinux/linux/issues/816
Signed-off-by: Nathan Chancellor
Reviewed-by: Bjorn Andersson
Signed-off-by: Kishon Vijay Abraham I -
In order to enforce suspend/resume ordering, this commit creates link
between phy consumers and phy devices. This link avoids to suspend phy
before phy consumers.Signed-off-by: Alexandre Torgue
[jonathanh@nvidia.com: Fix an abort when of_phy_get() returns error]
Signed-off-by: Jonathan Hunter
Signed-off-by: Kishon Vijay Abraham I
