12 Aug, 2015
1 commit
-
If for some reason the GPMC device hasn't been probed yet, gpmc_base is
going to be NULL. Because there's no context yet to be saved, just turn
these functions into no-ops until that device gets probed.Unable to handle kernel NULL pointer dereference at virtual address 00000010
pgd = c0204000
[00000010] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.2.0-rc5-next-20150804-05947-g23f38fe8eda9 #1
Hardware name: Generic OMAP3-GP (Flattened Device Tree)
task: c0e623e8 ti: c0e5c000 task.ti: c0e5c000
PC is at omap3_gpmc_save_context+0x8/0xc4
LR is at omap_sram_idle+0x154/0x23c
pc : [] lr : [] psr: 60000193
sp : c0e5df40 ip : c0f92a80 fp : c0999eb0
r10: c0e57364 r9 : c0e66f14 r8 : 00000003
r7 : 00000000 r6 : 00000003 r5 : 00000000 r4 : c0f5f174
r3 : c0fa4fe8 r2 : 00000000 r1 : 00000000 r0 : fa200280
Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c5387d Table: 80204019 DAC: 00000015
Process swapper/0 (pid: 0, stack limit = 0xc0e5c220)
Stack: (0xc0e5df40 to 0xc0e5e000)
df40: 00000000 c0e66ef8 c0f5f1a4 00000000 00000003 c02333a4 c3813822 00000000
df60: 00000000 c0e5a5c8 cfb8a5d0 c07f0c44 0e4f1d7e 00000000 00000000 00000000
df80: c3813822 00000000 cfb8a5d0 c0e5e4e4 cfb8a5d0 c0e66f14 c0e5a5c8 c0e5e54c
dfa0: c0e5e544 c0e57364 c0999eb0 c0277758 000000fa c0f5d000 00000000 c0d61c18
dfc0: ffffffff ffffffff 00000000 c0d61674 00000000 c0df7a48 00000000 c0f5d5d4
dfe0: c0e5e4c0 c0df7a44 c0e634f8 80204059 00000000 8020807c 00000000 00000000
[] (omap3_gpmc_save_context) from [] (omap_sram_idle+0x154/0x23c)
[] (omap_sram_idle) from [] (omap3_enter_idle_bm+0xec/0x1a8)
[] (omap3_enter_idle_bm) from [] (cpuidle_enter_state+0xbc/0x284)
[] (cpuidle_enter_state) from [] (cpu_startup_entry+0x174/0x24c)
[] (cpu_startup_entry) from [] (start_kernel+0x358/0x3c0)
[] (start_kernel) from [] (0x8020807c)
Code: c0ccace8 c0ccacc0 e59f30b4 e5932000 (e5921010)Signed-off-by: Tomeu Vizoso
Suggested-by: Javier Martinez Canillas
Reviewed-by: Javier Martinez Canillas
Acked-by: Roger Quadros
[tony@atomide.com: updated description as suggested by Javier]
Signed-off-by: Tony Lindgren
06 Jul, 2015
1 commit
27 Jun, 2015
1 commit
-
Pull ARM SoC driver updates from Kevin Hilman:
"Some of these are for drivers/soc, where we're now putting
SoC-specific drivers these days. Some are for other driver subsystems
where we have received acks from the appropriate maintainers.Some highlights:
- simple-mfd: document DT bindings and misc updates
- migrate mach-berlin to simple-mfd for clock, pinctrl and reset
- memory: support for Tegra132 SoC
- memory: introduce tegra EMC driver for scaling memory frequency
- misc. updates for ARM CCI and CCN busses"* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
drivers: soc: sunxi: Introduce SoC driver to map SRAMs
arm-cci: Add aliases for PMU events
arm-cci: Add CCI-500 PMU support
arm-cci: Sanitise CCI400 PMU driver specific code
arm-cci: Abstract handling for CCI events
arm-cci: Abstract out the PMU counter details
arm-cci: Cleanup PMU driver code
arm-cci: Do not enable CCI-400 PMU by default
firmware: qcom: scm: Add HDCP Support
ARM: berlin: add an ADC node for the BG2Q
ARM: berlin: remove useless chip and system ctrl compatibles
clk: berlin: drop direct of_iomap of nodes reg property
ARM: berlin: move BG2Q clock node
ARM: berlin: move BG2CD clock node
ARM: berlin: move BG2 clock node
clk: berlin: prepare simple-mfd conversion
pinctrl: berlin: drop SoC stub provided regmap
ARM: berlin: move pinctrl to simple-mfd nodes
pinctrl: berlin: prepare to use regmap provided by syscon
reset: berlin: drop arch_initcall initialization
...
02 Jun, 2015
2 commits
-
We support decoding the bootloader values if DEBUG is defined.
But we also need to change the struct omap_hwmod flags to have
HWMOD_INIT_NO_RESET to avoid the GPMC being reset during the
boot. Otherwise just the default timings will be displayed
instead of the bootloader configured timings.This also allows us to clean up the various GPMC related
hwmod flags. For debugging, we only need HWMOD_INIT_NO_RESET,
and HWMOD_INIT_NO_IDLE is not needed.Cc: Brian Hutchinson
Cc: Paul Walmsley
Cc: Roger Quadros
Signed-off-by: Tony Lindgren
Signed-off-by: Paul Walmsley -
We currently artificially limit the parsing of GPMC connected
devices based on the device name. Let's stop doing that, it's
confusing as adding devices to .dts files with using normal
names like fpga and usb will currently cause them to not probe.Cc: Roger Quadros
Reported-by: Brian Hutchinson
Signed-off-by: Tony Lindgren
13 May, 2015
1 commit
-
…egra/linux into next/drivers
Merge "ARM: tegra: Add EMC driver for v4.2-rc1" from Thierry Reding:
This introduces the EMC driver that's required to scale the external
memory frequency.* tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra: Add EMC frequency debugfs entry
memory: tegra: Add EMC (external memory controller) driver
memory: tegra: Add API needed by the EMC driver
of: Add Tegra124 EMC bindings
of: Document timings subnode of nvidia,tegra-mc
05 May, 2015
3 commits
-
This file in debugfs can be used to get or set the EMC frequency.
Reading the file will return the currently set frequency in Hz, while
writing the file sets the specified frequency rounded to the next
highest frequency supported by the board.Will be very useful when tuning memory scaling.
Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
[treding@nvidia.com: add "emc" debugfs directory]
Signed-off-by: Thierry Reding -
Implements functionality needed to change the rate of the memory bus
clock.Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
Signed-off-by: Thierry Reding -
The EMC driver needs to know the number of external memory devices and
also needs to update the EMEM configuration based on the new rate of the
memory bus.To know how to update the EMEM config, looks up the values of the burst
regs in the DT, for a given timing.Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
Signed-off-by: Thierry Reding
04 May, 2015
3 commits
-
As this interrupt is just for development purposes, as the TRM says, and
the sheer amount of interrupts fired can seriously disrupt userspace
when testing the lower frequencies supported by the EMC.From the TRM:
"There is one performance warning type interrupt: ARBITRATION_EMEM. It
fires when the MC detects that a request has been pending in the Row
Sorter long enough to hit the DEADLOCK_PREVENTION_SLACK_THRESHOLD. In
addition to true performance problems, this interrupt may fire in
situations such as clock-change where the EMC backpressures pending
traffic for long periods of time. This interrupt helps developers
identify and debug performance issues and configuration issues."Signed-off-by: Tomeu Vizoso
Signed-off-by: Thierry Reding -
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.Signed-off-by: Thierry Reding
-
Subsequent patches will add debugfs files that print the status of the
SWGROUPs. Add a new names field and complement the SoC tables with the
names of the individual SWGROUPs.Signed-off-by: Thierry Reding
23 Apr, 2015
1 commit
-
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for v4.1. Some of these are for drivers/soc, where we
find more and more SoC-specific drivers these days. Some are for
other driver subsystems where we have received acks from the
appropriate maintainers.The larger parts of this branch are:
- MediaTek support for their PMIC wrapper interface, a high-level
interface for talking to the system PMIC over a dedicated I2C
interface.- Qualcomm SCM driver has been moved to drivers/firmware. It's used
for CPU up/down and needs to be in a shared location for arm/arm64
common code.- cleanup of ARM-CCI PMU code.
- another set of cleanusp to the OMAP GPMC code"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
soc/mediatek: Remove unused variables
clocksource: atmel-st: select MFD_SYSCON
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs
arm-cci: Fix CCI PMU event validation
arm-cci: Split the code for PMU vs driver support
arm-cci: Get rid of secure transactions for PMU driver
arm-cci: Abstract the CCI400 PMU specific definitions
arm-cci: Rearrange code for splitting PMU vs driver code
drivers: cci: reject groups spanning multiple HW PMUs
ARM: at91: remove useless include
clocksource: atmel-st: remove mach/hardware dependency
clocksource: atmel-st: use syscon/regmap
ARM: at91: time: move the system timer driver to drivers/clocksource
ARM: at91: properly initialize timer
ARM: at91: at91rm9200: remove deprecated arm_pm_restart
watchdog: at91rm9200: implement restart handler
watchdog: at91rm9200: use the system timer syscon
mfd: syscon: Add atmel system timer registers definition
ARM: at91/dt: declare atmel,at91rm9200-st as a syscon
soc: qcom: gsbi: Add support for ADM CRCI muxing
...
27 Mar, 2015
1 commit
-
Add a driver for the NAND/External Memory Controller (NEMC) on JZ4780
and later SoCs.The primary function of this driver is to configure parameters, such
as timings, for external memory devices using data supplied in the
device tree. Devices connected to the NEMC are represented in the DT
as children of the NEMC node, the driver uses optional properties
specified in these child nodes to configure the parameters of each
bank.Signed-off-by: Alex Smith
Signed-off-by: Zubair Lutfullah Kakakhel
Signed-off-by: Greg Kroah-Hartman
06 Mar, 2015
8 commits
-
GPMC_CONFIG1_i parameters CLKACTIVATIONTIME and WAITMONITORINGTIME
have reserved values.
Raise an error if calculated timings try to program reserved values.GPMC_CONFIG1_i ATTACHEDDEVICEPAGELENGTH and DEVICESIZE were already checked
when parsing the DT.Explicitly comment invalid values on gpmc_cs_show_timings for
-CLKACTIVATIONTIME
-WAITMONITORINGTIME
-DEVICESIZE
-ATTACHEDDEVICEPAGELENGTHSigned-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles,
even though the access is defined as asynchronous, and no GPMC_CLK clock
is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider
for the GPMC clock, so it must be programmed to define the
correct WAITMONITORINGTIME delay.This patch correctly computes WAITMONITORINGTIME in GPMC_CLK cycles instead of GPMC_FCLK cycles,
both during programming (gpmc_cs_set_timings) and during retrieval (gpmc_cs_show_timings).Signed-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles,
even though the access is defined as asynchronous, and no GPMC_CLK clock
is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider
for the GPMC clock, so it must be programmed to define the
correct WAITMONITORINGTIME delay.Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
pure asynchronous accesses, i.e. both read and write asynchronous.Signed-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles,
even though the access is defined as asynchronous, and no GPMC_CLK clock
is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider
for the GPMC clock, so it must be programmed to define the
correct WAITMONITORINGTIME delay.Signed-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
DTS output was formatted to require additional work when copy-pasting into DTS.
Nano-second timings were replaced with interval of values that produce the same
number of clock ticks.Signed-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
GPMC debug output is aligned to 10 characters for field names.
However, some fields have bigger names, screwing up the alignment.
Consequently, alignment was changed to longest field name (17 chars) for now.Signed-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
This patch adds support for spawning buses as children of the GPMC.
Signed-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
OMAP2+ GPMC driver undefines DEBUG, which makes it unnecessarily
hard to turn DEBUG on. Remove the offending lines.Signed-off-by: Robert ABEL
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros
25 Feb, 2015
2 commits
-
Fix sparse warning:
warning: symbol 'gpmc_cs_get_name' was not declared. Should it be static?Signed-off-by: Semen Protsenko
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros -
Some GPMC_CONFIG7 register bits marked as "RESERVED", means they
shouldn't be overwritten. A typical approach to handle such bits called
"Read-Modify-Write". Writing procedure used in gpmc_cs_set_memconf()
utilizes RMW technique, but implemented incorrectly. Due to obvious typo
in code read register value is being rewritten by another value, which
leads to loss of read RESERVED bits. This patch fixes this.While at it, replace magic numbers with named constants to improve code
readability.Signed-off-by: Semen Protsenko
Acked-by: Tony Lindgren
Signed-off-by: Roger Quadros
30 Jan, 2015
1 commit
-
T1040 has a different version of corenet-cf, despite being incorrectly
labelled with a fsl,corenet2-cf compatible. The t1040 version of
corenet-cf has a version register that can be read to distinguish. The
t4240/b4860 version officially does not, but testing shows that it does
and has a different value, so use that. If somehow this ends up not
being reliable and we treat a t4240/b4860 as a t1040 (the reverse
should not happen, as t1040's version register is official), currently
the worst that should happen is writing to reserved bits to enable
events that don't exist.The changes to the t1040 version of corenet-cf that this driver cares
about are the addition of two new error events. There are also changes
to the format of cecar2, which is printed, but not interpreted, by this
driver.Signed-off-by: Scott Wood
18 Dec, 2014
1 commit
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Pull MTD updates from Brian Norris:
"Summary:
- Add device tree support for DoC3- SPI NOR:
Refactoring, for better layering between spi-nor.c and its
driver users (e.g., m25p80.c)New flash device support
Support 6-byte ID strings
- NAND:
New NAND driver for Allwinner SoC's (sunxi)GPMI NAND: add support for raw (no ECC) access, for testing
purposesAdd ATO manufacturer ID
A few odd driver fixes
- MTD tests:
Allow testers to compensate for OOB bitflips in oobtestFix a torturetest regression
- nandsim: Support longer ID byte strings
And more"
* tag 'for-linus-20141215' of git://git.infradead.org/linux-mtd: (63 commits)
mtd: tests: abort torturetest on erase errors
mtd: physmap_of: fix potential NULL dereference
mtd: spi-nor: allow NULL as chip name and try to auto detect it
mtd: nand: gpmi: add raw oob access functions
mtd: nand: gpmi: add proper raw access support
mtd: nand: gpmi: add gpmi_copy_bits function
mtd: spi-nor: factor out write_enable() for erase commands
mtd: spi-nor: add support for s25fl128s
mtd: spi-nor: remove the jedec_id/ext_id
mtd: spi-nor: add id/id_len for flash_info{}
mtd: nand: correct the comment of function nand_block_isreserved()
jffs2: Drop bogus if in comment
mtd: atmel_nand: replace memcpy32_toio/memcpy32_fromio with memcpy
mtd: cafe_nand: drop duplicate .write_page implementation
mtd: m25p80: Add support for serial flash Spansion S25FL132K
MTD: m25p80: fix inconsistency in m25p_ids compared to spi_nor_ids
mtd: spi-nor: improve wait-till-ready timeout loop
mtd: delete unnecessary checks before two function calls
mtd: nand: omap: Fix NAND enumeration on 3430 LDP
mtd: nand: add ATO manufacturer info
...
15 Dec, 2014
1 commit
-
Pull driver core update from Greg KH:
"Here's the set of driver core patches for 3.19-rc1.They are dominated by the removal of the .owner field in platform
drivers. They touch a lot of files, but they are "simple" changes,
just removing a line in a structure.Other than that, a few minor driver core and debugfs changes. There
are some ath9k patches coming in through this tree that have been
acked by the wireless maintainers as they relied on the debugfs
changes.Everything has been in linux-next for a while"
* tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits)
Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries"
fs: debugfs: add forward declaration for struct device type
firmware class: Deletion of an unnecessary check before the function call "vunmap"
firmware loader: fix hung task warning dump
devcoredump: provide a one-way disable function
device: Add dev__once variants
ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries
ath: use seq_file api for ath9k debugfs files
debugfs: add helper function to create device related seq_file
drivers/base: cacheinfo: remove noisy error boot message
Revert "core: platform: add warning if driver has no owner"
drivers: base: support cpu cache information interface to userspace via sysfs
drivers: base: add cpu_device_create to support per-cpu devices
topology: replace custom attribute macros with standard DEVICE_ATTR*
cpumask: factor out show_cpumap into separate helper function
driver core: Fix unbalanced device reference in drivers_probe
driver core: fix race with userland in device_add()
sysfs/kernfs: make read requests on pre-alloc files use the buffer.
sysfs/kernfs: allow attributes to request write buffer be pre-allocated.
fs: sysfs: return EGBIG on write if offset is larger than file size
...
10 Dec, 2014
1 commit
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Pull ARM SoC/OMAP GPMC driver cleanup and move from Arnd Bergmann:
"The GPMC driver has traditionally been considered a part of the OMAP
platform code and tightly interweaved with some of the boards.With this cleanup, it has finally come to the point where it makes
sense to move it out of arch/arm into drivers/memory, where we already
have other drivers for similar hardware. The cleanups are still
ongoing, with the goal of eventually having a standalone driver that
does not require an interface to architecture code.This is a separate branch because of dependencies on multiple other
branches, and to keep the drivers changes separate from the normal
cleanups"* tag 'omap-gpmc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
memory: gpmc: Move omap gpmc code to live under drivers
ARM: OMAP2+: Move GPMC initcall to devices.c
ARM: OMAP2+: Prepare to move GPMC to drivers by platform data header
ARM: OMAP2+: Remove unnecesary include in GPMC driver
ARM: OMAP2+: Drop board file for 3430sdp
ARM: OMAP2+: Drop board file for ti8168evm
ARM: OMAP2+: Drop legacy code for gpmc-smc91x.c
ARM: OMAP2+: Require proper GPMC timings for devices
ARM: OMAP2+: Show bootloader GPMC timings to allow configuring the .dts file
ARM: OMAP2+: Fix support for multiple devices on a GPMC chip select
ARM: OMAP2+: gpmc: Sanity check GPMC fck on probe
ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it
ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices
ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child()
ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()
04 Dec, 2014
1 commit
-
The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this driver (via a
custom API or a generic subsystem) to allow clients to register latency
requirements.This driver also registers an IOMMU (SMMU) that's implemented by the
memory controller. It is supported on Tegra30, Tegra114 and Tegra124
currently. Tegra20 has a GART instead.The Tegra SMMU operates on memory clients and SWGROUPs. A memory client
is a unidirectional, special-purpose DMA master. A SWGROUP represents a
set of memory clients that form a logical functional unit corresponding
to a single device. Typically a device has two clients: one client for
read transactions and one client for write transactions, but there are
also devices that have only read clients, but many of them (such as the
display controllers).Because there is no 1:1 relationship between memory clients and devices
the driver keeps a table of memory clients and the SWGROUPs that they
belong to per SoC. Note that this is an exception and due to the fact
that the SMMU is tightly integrated with the rest of the Tegra SoC. The
use of these tables is discouraged in drivers for generic IOMMU devices
such as the ARM SMMU because the same IOMMU could be used in any number
of SoCs and keeping such tables for each SoC would not scale.Acked-by: Joerg Roedel
Signed-off-by: Thierry Reding
29 Nov, 2014
1 commit
-
Just move to drivers as further clean-up can now happen there
finally.Let's also add Roger and me to the MAINTAINERS so we get
notified for any patches related to GPMC.Cc: Arnd Bergmann
Acked-by: Roger Quadros
Signed-off-by: Tony Lindgren
06 Nov, 2014
1 commit
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Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.Signed-off-by: Aaron Sierra
Signed-off-by: Brian Norris
20 Oct, 2014
1 commit
-
A platform_driver does not need to set an owner, it will be populated by the
driver core.Signed-off-by: Wolfram Sang
25 Aug, 2014
1 commit
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Pull AT91 reset, poweroff and ram drivers from Maxime Ripard:
"This tag holds the various new drivers introduced to move code that used to be
in mach-at91 over to the proper frameworks.These files are the reboot and poweroff code for all AT91 SoCs but the RM9200,
and the ram controller driver is not doing much at the time, except for grabing
the RAM clock in order to leave it always enabled."Conflicts:
arch/arm/mach-at91/Kconfig
30 Jul, 2014
1 commit
-
The CoreNet Coherency Fabric is part of the memory subsystem on
some Freescale QorIQ chips. It can report coherency violations (e.g.
due to misusing memory that is mapped noncoherent) as well as
transactions that do not hit any local access window, or which hit a
local access window with an invalid target ID.Signed-off-by: Scott Wood
Reviewed-by: Bharat Bhushan
15 Jul, 2014
1 commit
-
Atmel SoCs have one or multiple RAM controllers that need one or multiple clocks
to run.
This driver handle those clocks.Signed-off-by: Alexandre Belloni
Signed-off-by: Maxime Ripard
Acked-by: Nicolas Ferre
29 Apr, 2014
5 commits
-
Currently, the mvebu-devbus Device Tree binding makes defining the
timing parameters mandatory.However, in practice, when converting Orion5x platforms to the Device
Tree, we may not necessarily have easy access to the hardware
platforms to fetch those values which were not defined in old-style
board files: all these platforms rely on the bootloader setting the
timing parameters correctly.In order to facilitate the migration to the Device Tree of this
platform, this commit relaxes the mvebu-devbus Device Tree binding by
introducing a 'devbus,keep-config' boolean property, which, if
defined, will ignore all timing parameters passed in the Device Tree,
and simply rely on the timing values already defined by the
bootloader.Signed-off-by: Thomas Petazzoni
Acked-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Link: https://lkml.kernel.org/r/1398202002-28530-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper -
This commit adds support for the Orion5x family of Marvell processors
into the mvebu-devbus driver. It differs from the already supported
Armada 370/XP by:* Having a single register (instead of two) for doing all the timing
configuration.* Having a few less timing configuration parameters.
For this reason, a separate compatible string "marvell,orion-devbus"
is introduced.Signed-off-by: Thomas Petazzoni
Acked-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Link: https://lkml.kernel.org/r/1398202002-28530-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper -
The mvebu-devbus driver currently only supports the Armada 370/XP
family, but it can also cover the Orion5x family. However, the Orion5x
family has a different organization of the registers.Therefore, in preparation to the introduction of Orion5x support, we
separate into two functions the code that 1/ retrieves the timing
parameters from the Device Tree and 2/ applies those timings
parameters into the hardware registers.Signed-off-by: Thomas Petazzoni
Acked-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Link: https://lkml.kernel.org/r/1398202002-28530-8-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper -
As noted by Sebastian Hesselbarth, the definitions in mvebu-devbus.c
are not bit definition, but rather shift values, so a _SHIFT prefix
would make more sense. This commit therefore replaces the *_BIT
definitions by *_SHIFT definitions.Signed-off-by: Thomas Petazzoni
Acked-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Link: https://lkml.kernel.org/r/1398202002-28530-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper -
The mvebu-devbus driver currently only supports the Armada 370/XP
family, but it can also cover the Orion5x family. However, the Orion5x
family has a different organization of the register. Therefore, in
preparation to the introduction of Orion5x support, we rename the
Armada 370/XP specific definitions to have an ARMADA_ prefix.Signed-off-by: Thomas Petazzoni
Acked-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Link: https://lkml.kernel.org/r/1398202002-28530-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper
