30 Oct, 2013
40 commits
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The S/PDIF driver needs regmap so select it to make sure it gets
included in the build.Reported-by: Fengguang Wu
Acked-by: Nicolin Chen
Signed-off-by: Mark Brown
Signed-off-by: Nicolin Chen -
ASRC and HDMI audio might meet unexpected stop, 'ctrl+z' for example,
and then disable its sdma channel. But after 'fg' resume, because sdma
channel's status has already been set into DMA_ERROR, we need to prepare
dmaengine again to clear its error state, otherwise sdma driver would
bypass its channel enabling and 'Input/Output error' would happen to
ALSA lib.
The combined prepare and submit are also being used in soc-dmaengine,
the common ASoC dmaengine driver.And since we already use a proper way to handle sdma channel status,
there's no need to make an exception for HDMI any more, so drop it.Signed-off-by: Nicolin Chen
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'params' might be confused with snd_pcm_hw_params, so use 'priv' instead.
Signed-off-by: Nicolin Chen
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asrc_isr() is mainly used to detect and record overload error,
so we add some print massage to make it easy to debug.Also fixed an incorrect function name -- dev_debug() by using
the correct one -- dev_dbg() in dump_regs().Signed-off-by: Nicolin Chen
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Added a new bus freq mode - ultra_low_bus_freq_mode.
In this mode the ARM is the only bus master that is active and
the system is already in low power idle mode.
And when ARM executes WFI in this mode, we do some aggressive
power savings techinques like:
1. Drop DDR freq to 1MHz
2. Drop AHB freq to 3MHz
3. Float the DDR IO pads
4. If all PLLs are in bypass (which should be the case), do
some analog power saving options like reducing the OSC-bias current,
turning off the regular bandgap, disabling the regular 2P5, enabling
the weak 2p5 etc.Signed-off-by: Ranjani Vaidyanathan
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Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAC address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.Signed-off-by: Fugang Duan
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- After probe, disable all clocks incluing ipg, ahb, enet_out, ptp clock.
- Open ethx interface enable necessary clocks.
Close ethx interface disable all clocks.
- Correct the MDIO clock source.Signed-off-by: Fugang Duan
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Current imx6sl dts define enet_ref clock as ipg clock, which is not
right. The ipg clock is "IMX6SL_CLK_ENET" defined at imx6sl-clock.h.Signed-off-by: Fugang Duan
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There's a enet clock gate missing in clock tree, thus add it.
Signed-off-by: Fugang Duan
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Use generic dmaengine_prep_dma_cyclic() in imx-hdmi-dma.c and fsl-asrc.c
Signed-off-by: Nicolin Chen
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Previously, we used sdma's event pending to forcibly re-schedule sdma
for work round, because sdma channel for ASRC input task would fail to
be opened due to its dma request always keeping high after ASRC opens
the pair, which cause sdma miss the trigger point of dma request.Now, instead of using event pending, we clear the dma request on ASRC
driver side by setting its thresholds to an impossible trigger area
during its stall state. Since ASRC would stall its process when input
fifo is near empty or output fifo is near full, during the stall state,
the specific thresholds, 0 for input fifo and 63 for output fifo, would
never let asrc meet this condition. So dma request can be cleared and
raised again after we restore the true required thresholds.Accordingly, since we don't need event pending any more, we dropped the
code from the sdma driver.Signed-off-by: Nicolin Chen
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Add polling mode for data transmitting without dma support for debugging when
sdma may have issue.Signed-off-by: Nicolin Chen
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We don't need to set ASRC to STALL level everytime, instead we only need
to do that at the beginning. If we insert null data into input fifo during
the sequence of valid datas, there would be a noise occur to it.By doing this, we can assure ASRC would keep each period's perturbation of
output dma task within 8 sample sizes, which is the default value for last
period number. Thus we don't need to expand the last period number any more.This patch also dropped some unused functions since the driver no long needs
them and replaced wrapped function for channel number configuration with direct
regmap_update_bits() to make the driver clean.Signed-off-by: Nicolin Chen
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We can determine the IP version from DT compatible name to decide which
clock map and channel bits should be used.Signed-off-by: Nicolin Chen
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* Dropped unused header files.
* Use pair-explicit error massage.
* Fixed some coding style issue.Signed-off-by: Nicolin Chen
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Use completion instead of counter to make driver clean and drop
implicit mdelay by using wait_for_completion().Signed-off-by: Nicolin Chen
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Dropped the legency readl/writel() and use regmap instead. Also removed
core clock's clk_prepare() and spin_lock()/unlock() outside regmap due to
regmap already has these features.This patch also added a missing writable register to the regmap in order
to assure the regsiter updating success.Signed-off-by: Nicolin Chen
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Set the priority as what kernel 3.0.35 does to keep it safe.
Signed-off-by: Nicolin Chen
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ASRC is using shp_2_mcu and mcu_2_shp sdma scripts that use spba bus to
transfer data, while the driver hasn't include the control code of spba
clock.This would cause multiple pair conversion failed in most of time. Thus
we need to add its support.Signed-off-by: Nicolin Chen
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regmap-mmio uses a spinlock with spin_lock() and spin_unlock() for locking.
To be able to use the regmap API from different contexts (atomic vs non-atomic),
without the risk of race conditions, we need to use spin_lock_irqsave() and
spin_lock_irqrestore() instead. A new field, the spinlock_flags field, is added
to regmap struct to store the flags between regmap_{,un}lock_spinlock(). The
spinlock_flags field itself is also protected by the spinlock.Thanks to Stephen Warren for the suggestion of this particular solution.
Signed-off-by: Lars-Peter Clausen
Reviewed-by: Stephen Warren
Signed-off-by: Mark Brown
Signed-off-by: Nicolin Chen -
Enable net VLAN 8021Q in imx_v7_defconfig.
Signed-off-by: Fugang Duan
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i.MX6 I2C clk is from IPG_PERCLK which is sourced from IPG_CLK.
Under normal operation, IPG_CLK is 66MHz, ipg_perclk is at 22MHz.
In low bus freq mode, IPG_CLK is at 12MHz and IPG_PERCLK is down
to 4MHz. So the I2C driver must update the divider register for
each transaction when the current IPG_PERCLK is not equal to the
clock of previous transaction.Signed-off-by: Fugang Duan
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The naming convention for power supply node in DTS is "%s-supply".
With this patch regulator_get() will process in the DT way rather than
traditional way. This patch has no functional impact.Signed-off-by: Robby Cai
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The overlay framebuffer's position and resolution are
set with two different APIs. They depend on each other to
make sure the overlay framebuffer window will not go out
of the background framebuffer window. Potentially, this
causes the overlay framebuffer's position or resolution
of the current video pipeline be impacted by the settings
of the last time. To setup the overlay fb from scratch
correctly, this patch takes the following steps:
- blank framebuffer
- set framebuffer position to the starting point
- reconfigure framebuffer
- set framebuffer position to a specific point
- unblank framebuffer
This procedure applies to non-overlay framebuffers as well.Signed-off-by: Liu Ying
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Users may call VIDIOC_S_CTRL or VIDIOC_S_CROP ioctrls
to update streaming parameters on-the-fly after video
has been streamed on, such as for rotation/output
resolution/overlay output position change. Any
unnecessary frame buffer reconfiguration would cause
a pair of frame buffer blank/unblank events happen and
even makes the background framebuffer show up for a
short period of time if the video is rendered on an
overlay framebuffer. This patch compares the last time
video output pipe line settings with the current ones
to determine whether frame buffer reconfiguration is
necessary or not.Signed-off-by: Liu Ying
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NOTE since SD Card in main board takes a long route hence with
Drive Speed High 80 OHMS causing error on high speed cards.
Per suggestion DSE 40 OHMS is used.Signed-off-by: Dong Aisheng
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After finish video playback, the last frame remains on the display.
It's because the UI display start address (smem_start) has been changed when
do video playback but not changed back again after the playback finishes.
From the function call point of view,pxp_set_fbinfo() // pxp->fb.base tracks right addr for UI framebuffer
pxp_show_buf(toshow) // smem_start changed to v4l2 display addr
pxp_set_fbinfo() // pxp->fb.base changed to v4l2 display addr
pxp_show_buf(not toshow) // smem_start still equal to v4l2 display addr
// for pan_displayThis patch fixes it by calling pxp_set_fbinfo once in open function.
Signed-off-by: Robby Cai
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This patch fixes 4 issues:
1. Add the .align 8 directive to the LPDDR2 freq change code,
else the fncpy() function fails and the kernel does not boot.
2. Loads the correct L2_BASE_ADDR into register in lpddr2 freq change code
3. Fix the warning in clk_imx6sl.c
4. Change dev_WARN to dev_info in busfreq-imx6.c.Signed-off-by: Ranjani Vaidyanathan
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Remove HDCP register define from HDMI kernel driver.
Signed-off-by: Sandor Yu
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Remove HDCP register access from HDMI driver.
Signed-off-by: Sandor Yu
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The ecspi1 has pin conflict with the i2c3.
This patch adds two dts files for the ECSPI support.Signed-off-by: Huang Shijie
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This patch handles downsize ratio overflow error by doing
input cropping with 8 pixel step.Signed-off-by: Liu Ying
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IPUv3 IC task downsize scaling ratio cannot exceed or be
equal to 8:1. This patch makes the code return error code
if the ratio overflows.Signed-off-by: Liu Ying
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This patch improves IPU IC task scale check logic
so that we may return with error code if the calculation
for scale coefficients fails.Signed-off-by: Liu Ying
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Fix the code to report correct PFD and PLL clock rates when
the PLL is in bypass state.Signed-off-by: Ranjani Vaidyanathan
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Change dtsi files to enable busfreq support.
Signed-off-by: Ranjani Vaidyanathan
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Add support to scale the DDR frequency between 400MHz and 24MHz.
Add support to scale AHB between 132MHz and 24MHz.Signed-off-by: Ranjani Vaidyanathan
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This patch makes mmapped video buffers bufferable so that software
decoders may render the video buffers efficiently.Signed-off-by: Liu Ying
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The patch "0b7a76a ARM: dts: imx6q{dl}: add DTE pads for uart"
adds the DTE pads for uart. For PAD_EIM_D29, the offset of the
Pad Mux register should be 0x0c8, not 0x0c4.This patch fixes it.
Signed-off-by: Huang Shijie
Signed-off-by: Shawn Guo -
enable the uart2 for imx6q-arm2 board.
The uart2 works in the DTE mode, with the RTS/CTS and DMA enabled.Signed-off-by: Huang Shijie
Signed-off-by: Shawn Guo
