12 Dec, 2020
1 commit
-
…pub/scm/linux/kernel/git/mtd/linux") into android-mainline
Steps on the way to 5.10-final
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Iaf246e292babee342e89c090dad69e12e2cb4d75
09 Dec, 2020
1 commit
-
Mistakenly the buffers (input and output) become enabled together for a short
period of time during GPIO request. This is problematic, because instead of
initial motive to disable them in the commit af7e3eeb84e2
("pinctrl: intel: Disable input and output buffer when switching to GPIO"),
the driven value on the pin, which might be used as an IRQ line, brings
firmwares of some touch pads to an awkward state that needs a full power off
to recover. Fix this, as stated in the culprit commit, by disabling the buffers.Fixes: af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO")
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=210497
Reported-by: Pierre-Louis Bossart
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
Tested-by: Pierre-Louis Bossart
Tested-by: Kai-Heng Feng
Link: https://lore.kernel.org/r/20201208182403.40435-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij
08 Dec, 2020
1 commit
-
Commit 6726fbff19bf ("pinctrl: aspeed: Fix GPI only function problem.")
fixes access to GPIO banks T and U on the AST2600. Both banks contain
input-only pins and the GPIO pin function is named GPITx and GPIUx
respectively. Unfortunately the fix had a negative impact on GPIO banks
D and E for the AST2400 and AST2500 where the GPIO pass-through
functions take similar "GPI"-style names. The net effect on the older
SoCs was that when the GPIO subsystem requested a pin in banks D or E be
muxed for GPIO, they were instead muxed for pass-through mode.
Mistakenly muxing pass-through mode e.g. breaks booting the host on
IBM's Witherspoon (AC922) platform where GPIOE0 is used for FSI.Further exploit the names in the provided expression structure to
differentiate pass-through from pin-specific GPIO modes.This follow-up fix gives the expected behaviour for the following tests:
Witherspoon BMC (AST2500):
1. Power-on the Witherspoon host
2. Request GPIOD1 be muxed via /sys/class/gpio/export
3. Request GPIOE1 be muxed via /sys/class/gpio/export
4. Request the balls for GPIOs E2 and E3 be muxed as GPIO pass-through
("GPIE2" mode) via a pinctrl hog in the devicetreeRainier BMC (AST2600):
5. Request GPIT0 be muxed via /sys/class/gpio/export
6. Request GPIU0 be muxed via /sys/class/gpio/exportTogether the tests demonstrate that all three pieces of functionality
(general GPIOs via 1, 2 and 3, input-only GPIOs via 5 and 6, pass-through
mode via 4) operate as desired across old and new SoCs.Fixes: 9b92f5c51e9a ("pinctrl: aspeed: Fix GPI only function problem.")
Signed-off-by: Andrew Jeffery
Tested-by: Joel Stanley
Reviewed-by: Joel Stanley
Cc: Billy Tsai
Cc: Joel Stanley
Link: https://lore.kernel.org/r/20201126063337.489927-1-andrew@aj.id.au
Signed-off-by: Linus Walleij
04 Dec, 2020
1 commit
-
Debounce filter setting should be independent from IRQ type setting
because according to the ACPI specs, there are separate arguments for
specifying debounce timeout and IRQ type in GpioIo() and GpioInt().Together with commit 06abe8291bc31839950f7d0362d9979edc88a666
("pinctrl: amd: fix incorrect way to disable debounce filter") and
Andy's patch "gpiolib: acpi: Take into account debounce settings" [1],
this will fix broken touchpads for laptops whose BIOS set the
debounce timeout to a relatively large value. For example, the BIOS
of Lenovo AMD gaming laptops including Legion-5 15ARH05 (R7000),
Legion-5P (R7000P) and IdeaPad Gaming 3 15ARH05, set the debounce
timeout to 124.8ms. This led to the kernel receiving only ~7 HID
reports per second from the Synaptics touchpad
(MSFT0001:00 06CB:7F28).Existing touchpads like [2][3] are not troubled by this bug because
the debounce timeout has been set to 0 by the BIOS before enabling
the debounce filter in setting IRQ type.[1] https://lore.kernel.org/linux-gpio/20201111222008.39993-11-andriy.shevchenko@linux.intel.com/
8dcb7a15a585 ("gpiolib: acpi: Take into account debounce settings")
[2] https://github.com/Syniurge/i2c-amd-mp2/issues/11#issuecomment-721331582
[3] https://forum.manjaro.org/t/random-short-touchpad-freezes/30832/28Signed-off-by: Coiby Xu
Reviewed-by: Andy Shevchenko
Cc: Hans de Goede
Cc: Andy Shevchenko
Cc: Benjamin Tissoires
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/linux-gpio/CAHp75VcwiGREBUJ0A06EEw-SyabqYsp%2Bdqs2DpSrhaY-2GVdAA%40mail.gmail.com/
BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1887190
Link: https://lore.kernel.org/r/20201125130320.311059-1-coiby.xu@gmail.com
Signed-off-by: Linus Walleij
18 Nov, 2020
1 commit
-
…t/pinctrl/intel into fixes
intel-pinctrl for v5.10-3
* Fix HOSTSW_OWN offset and unhide SPI group of pins on Jasper Lake
* Fix debounce configuration on Baytrail when it's turned off
* Fix default bias setting on MerrifieldThe following is an automated git shortlog grouped by driver:
baytrail:
- Avoid clearing debounce value when turning it offjasperlake:
- Fix HOSTSW_OWN offset
- Unhide SPI group of pinsmerrifield:
- Set default bias in case no particular value given
16 Nov, 2020
4 commits
-
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.Fixes: 658b476c742f ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d66 ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1d5 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.Fixes: e278dcb7048b1 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green
Acked-by: Mika Westerberg
Signed-off-by: Andy Shevchenko -
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
14 Nov, 2020
1 commit
-
…m/fs/xfs/xfs-linux") into android-mainline
Steps on the way to 5.10-rc4
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Iba36d2244c4229d44e3d391ed23dc25c6022f917
10 Nov, 2020
5 commits
-
…it/pinctrl/intel into fixes
intel-pinctrl for v5.10-2
* Respect bias setting when comes from ACPI
The following is an automated git shortlog grouped by driver:
intel:
- Set default bias in case no particular value given
- Fix 2 kOhm bias which is 833 Ohm -
Specify the PDC mapping for SM8250, so that gpio interrupts are
propertly mapped to the wakeup IRQs of the PDC.Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.")
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20201028043642.1141723-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij -
When GPIOs that are routed to PDC are used as output they can still latch
the IRQ pending at GIC. As a result the spurious IRQ was handled when the
client driver change the direction to input to starts using it as IRQ.Currently such erroneous latched IRQ are cleared with .irq_enable callback
however if the driver continue to use GPIO as interrupt and invokes
disable_irq() followed by enable_irq() then everytime during enable_irq()
previously latched interrupt gets cleared.This can make edge IRQs not seen after enable_irq() if they had arrived
after the driver has invoked disable_irq() and were pending at GIC.Move clearing erroneous IRQ to .irq_request_resources callback as this is
the place where GPIO direction is changed as input and its locked as IRQ.While at this add a missing check to invoke msm_gpio_irq_clear_unmask()
from .irq_enable callback only when GPIO is not routed to PDC.Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah
Link: https://lore.kernel.org/r/1604561884-10166-1-git-send-email-mkshah@codeaurora.org
Signed-off-by: Linus Walleij -
RTC is 32.768kHz thus 512 RtcClk equals 15625 usec. The documentation
likely has dropped precision and that's why the driver mistakenly took
the slightly deviated value.Cc: stable@vger.kernel.org
Reported-by: Andy Shevchenko
Suggested-by: Andy Shevchenko
Suggested-by: Hans de Goede
Signed-off-by: Coiby Xu
Reviewed-by: Andy Shevchenko
Reviewed-by: Hans de Goede
Link: https://lore.kernel.org/linux-gpio/2f4706a1-502f-75f0-9596-cc25b4933b6c@redhat.com/
Link: https://lore.kernel.org/r/20201105231912.69527-3-coiby.xu@gmail.com
Signed-off-by: Linus Walleij -
The correct way to disable debounce filter is to clear bit 5 and 6
of the register.Cc: stable@vger.kerne.org
Signed-off-by: Coiby Xu
Reviewed-by: Hans de Goede
Cc: Hans de Goede
Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/
Link: https://lore.kernel.org/r/20201105231912.69527-2-coiby.xu@gmail.com
Signed-off-by: Linus Walleij
05 Nov, 2020
3 commits
-
Some gpio pin at aspeed soc is input only and the prefix name of these
pin is "GPI" only.
This patch fine-tune the condition of GPIO check from "GPIO" to "GPI"
and it will fix the usage error of banks D and E in the AST2400/AST2500
and banks T and U in the AST2600.Fixes: 4d3d0e4272d8 ("pinctrl: Add core support for Aspeed SoCs")
Signed-off-by: Billy Tsai
Reviewed-by: Andrew Jeffery
Link: https://lore.kernel.org/r/20201030055450.29613-1-billy_tsai@aspeedtech.com
Signed-off-by: Linus Walleij -
It is useful for debugging to have the error message printed
when regmap initialisation fails. Add it to the driver.Signed-off-by: Andy Shevchenko
Cc: Martin Hundebøll
Link: https://lore.kernel.org/r/20201009180856.4738-2-andriy.shevchenko@linux.intel.com
Tested-by: Jan Kundrát
Signed-off-by: Linus Walleij -
It appears that simplification of mcp23s08_spi_regmap_init() made
a regression due to wrong size calculation for dev_kmemdup() call.
It misses the fact that config variable is already a pointer, thus
the sizeof() calculation is wrong and only 4 or 8 bytes were copied.Fix the parameters to devm_kmemdup() to copy a full chunk of memory.
Fixes: 0874758ecb2b ("pinctrl: mcp23s08: Refactor mcp23s08_spi_regmap_init()")
Reported-by: Martin Hundebøll
Signed-off-by: Andy Shevchenko
Tested-by: Martin Hundebøll
Link: https://lore.kernel.org/r/20201009180856.4738-1-andriy.shevchenko@linux.intel.com
Tested-by: Jan Kundrát
Signed-off-by: Linus Walleij
04 Nov, 2020
2 commits
-
Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mappingThis patch can speed up system boot on, also abandon many unused irq
mappings' create.Signed-off-by: Jianqun Xu
Reviewed-by: Heiko Stuebner
Reviewed-by: Kever Yang
Link: https://lore.kernel.org/r/20201013063731.3618-4-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij -
There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.Signed-off-by: Jianqun Xu
Reviewed-by: Heiko Stuebner
Reviewed-by: Kever Yang
Link: https://lore.kernel.org/r/20201013063731.3618-3-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij
28 Oct, 2020
1 commit
-
The values for the SSI pins on GPIO chips D and E were off by 0x20.
Fixes: d3ef8c6b2286 ("pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780.")
Signed-off-by: Paul Cercueil
Reported-by: Artur Rojek
Link: https://lore.kernel.org/r/20201010192509.9098-1-paul@crapouillou.net
Reviewed-by: 周琰杰 (Zhou Yanjie)
Signed-off-by: Linus Walleij
26 Oct, 2020
3 commits
-
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.In case of Intel pin control hardware the 5 kOhm sounds plausible
because on one hand it's a minimum of resistors present in all
hardware generations and at the same time it's high enough to minimize
leakage current (will be only 200 uA with the above choice).Fixes: e57725eabf87 ("pinctrl: intel: Add support for hardware debouncer")
Reported-by: Jamie McClymont
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
2 kOhm bias was never an option in Intel GPIO hardware, the available
matrix is:000 none
001 1 kOhm (if available)
010 5 kOhm
100 20 kOhmAs easy to get the 3 resistors are gated separately and according to
parallel circuits calculations we may get combinations of the above where
the result is always strictly less than minimal resistance. Hence,
additional values can be:011 ~833.3 Ohm
101 ~952.4 Ohm
110 ~4 kOhm
111 ~800 OhmThat said, convert TERM definitions to be the bit masks to reflect the above.
While at it, enable the same setting for pull down case.
Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
Cc: Jamie McClymont
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
…inux/kernel/git/gregkh/spdx") into android-mailine
Steps on the way to 5.10-rc1
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ifd6acb7037073d3b8411647e2087aa0df71c8830
23 Oct, 2020
1 commit
-
…nux/kernel/git/linusw/linux-gpio") into android-mainline
Steps on the way to 5.10-rc1
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I7395903c218c84b8d629829069690a8f9f618f58
21 Oct, 2020
1 commit
-
…/scm/linux/kernel/git/tip/tip") into android-mainline
Steps on the way to 5.10-rc1
Change-Id: I2008d31f1f4c3ba4325ae536ad95b66b94f81601
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
15 Oct, 2020
1 commit
-
Pull pin control updates from Linus Walleij:
"Core changes:- NONE whatsoever, we don't even touch the core files this time
around.New drivers:
- New driver for the Toshiba Visconti SoC.
- New subdriver for the Qualcomm MSM8226 SoC.
- New subdriver for the Actions Semiconductor S500 SoC.
- New subdriver for the Mediatek MT8192 SoC.
- New subdriver for the Microchip SAMA7G5 SoC.
Driver enhancements:
- Intel Cherryview and Baytrail cleanups and refactorings.
- Enhanced support for the Renesas R8A7790, more pins and groups.
- Some optimizations for the MCP23S08 MCP23x17 variant.
- Some cleanups around the Actions Semiconductor subdrivers.
- A bunch of cleanups around the SH-PFC and Emma Mobile drivers.
- The "SH-PFC" (literally SuperH pin function controller, I think)
subdirectory is now renamed to the more neutral "renesas", as these
are not very much centered around SuperH anymore.- Non-critical fixes for the Aspeed driver.
- Non-critical fixes for the Ingenic (MIPS!) driver.
- Fix a bunch of missing pins on the AMD pinctrl driver"
* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits)
pinctrl: amd: Add missing pins to the pin group list
dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI
pinctrl: mediatek: Free eint data on failure
pinctrl: single: fix debug output when #pinctrl-cells = 2
pinctrl: single: fix pinctrl_spec.args_count bounds check
pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
pinctrl: tigerlake: Fix register offsets for TGL-H variant
pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2
pinctrl: mediatek: use devm_platform_ioremap_resource_byname()
pinctrl: nuvoton: npcm7xx: Constify static ops structs
pinctrl: mediatek: mt7622: add antsel pins/groups
pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register()
pinctrl: at91-pio4: add support for sama7g5 SoC
dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5
pinctrl: spear: simplify the return expression of tvc_connect()
pinctrl: spear: simplify the return expression of spear310_pinctrl_probe
pinctrl: sprd: use module_platform_driver to simplify the code
pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.
...
14 Oct, 2020
1 commit
-
Pull GPIO updates from Linus Walleij:
"This time very little driver changes but lots of core changes.We have some interesting cooperative work for ARM and Intel alike,
making the GPIO subsystem more and more suitable for industrial
systems and the like, in addition to the in-kernel users.We touch driver core (device properties) and lib/* by adding one
simple string array free function, these are authored by Andy
Shevchenko who is a well known and recognized core helpers maintainers
so this should be fine.We also see some Android GKI-related modularization in the MXC
drivers.Core changes:
- The big core change is the updated (v2) userspace character device
API.This corrects badly designed 64-bit alignment around the line
events. We also add the debounce request feature. This echoes the
often quotes passage from Frederick Brooks "The mythical man-month"
to always throw one away, which we have seen before in things such
as V4L2. So we put in a new one and deprecate and obsolete the old
one.- All example tools in tools/gpio/* are migrated to the new API to
set a good example. The libgpiod userspace library has been
augmented to use this new API pretty much from day 1.- Some misc API hardening by using strn* function calls has been
added as well.- Use the simpler IDA interface for GPIO chip instance enumeration.
- Add device core function for counting string arrays in device
properties.- Provide a generic library function kfree_strarray() that can be
used throughout the kernel.Driver enhancements:
- The DesignWare dwapb-gpio driver has been enhanced and now uses the
IRQ handling in the gpiolib core.- The mockup and aggregator drivers have seen some substantial code
clean-up and now use more of the core kernel inftrastructure.- Misc cleanups using dev_err_probe().
- The MXC drivers (Freescale/NXP) can now be built modularized, which
makes modularized GKI Android kernels happy"* tag 'gpio-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (73 commits)
gpiolib: Update header block in gpiolib-cdev.h
gpiolib: cdev: switch from kstrdup() to kstrndup()
docs: gpio: add a new document to its index.rst
gpio: pca953x: Add support for the NXP PCAL9554B/C
tools: gpio: add debounce support to gpio-event-mon
tools: gpio: add multi-line monitoring to gpio-event-mon
tools: gpio: port gpio-event-mon to v2 uAPI
tools: gpio: port gpio-hammer to v2 uAPI
tools: gpio: rename nlines to num_lines
tools: gpio: port gpio-watch to v2 uAPI
tools: gpio: port lsgpio to v2 uAPI
gpio: uapi: document uAPI v1 as deprecated
gpiolib: cdev: support setting debounce
gpiolib: cdev: support GPIO_V2_LINE_SET_VALUES_IOCTL
gpiolib: cdev: support GPIO_V2_LINE_SET_CONFIG_IOCTL
gpiolib: cdev: support edge detection for uAPI v2
gpiolib: cdev: support GPIO_V2_GET_LINEINFO_IOCTL and GPIO_V2_GET_LINEINFO_WATCH_IOCTL
gpiolib: cdev: support GPIO_V2_GET_LINE_IOCTL and GPIO_V2_LINE_GET_VALUES_IOCTL
gpiolib: add build option for CDEV v1 ABI
gpiolib: make cdev a build option
...
13 Oct, 2020
1 commit
-
Pull irq updates from Thomas Gleixner:
"Updates for the interrupt subsystem:Core:
- Allow trimming of interrupt hierarchy to support odd hardware
setups where only a subset of the interrupts requires the full
hierarchy.- Allow the retrigger mechanism to follow a hierarchy to simplify
driver code.- Provide a mechanism to force enable wakeup interrrupts on suspend.
- More infrastructure to handle IPIs in the core code
Architectures:
- Convert ARM/ARM64 IPI handling to utilize the interrupt core code.Drivers:
- The usual pile of new interrupt chips (MStar, Actions Owl, TI
PRUSS, Designware ICTL)- ARM(64) IPI related conversions
- Wakeup support for Qualcom PDC
- Prevent hierarchy corruption in the NVIDIA Tegra driver
- The usual small fixes, improvements and cleanups all over the
place"* tag 'irq-core-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits)
dt-bindings: interrupt-controller: Add MStar interrupt controller
irqchip/irq-mst: Add MStar interrupt controller support
soc/tegra: pmc: Don't create fake interrupt hierarchy levels
soc/tegra: pmc: Allow optional irq parent callbacks
gpio: tegra186: Allow optional irq parent callbacks
genirq/irqdomain: Allow partial trimming of irq_data hierarchy
irqchip/qcom-pdc: Reset PDC interrupts during init
irqchip/qcom-pdc: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
genirq/PM: Introduce IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
pinctrl: qcom: Use return value from irq_set_wake() call
pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags
ARM: Handle no IPI being registered in show_ipi_list()
MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller
irqchip: Add Actions Semi Owl SIRQ controller
dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
dt-bindings: dw-apb-ictl: Update binding to describe use as primary interrupt controller
irqchip/dw-apb-ictl: Add primary interrupt controller support
irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domains
genirq: Add stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER
...
07 Oct, 2020
3 commits
-
Some of the pins were not exposed in the initial driver or kept as
reserved. Exposing all of them now.Signed-off-by: Shyam Sundar S K
Link: https://lore.kernel.org/r/20201007111220.744348-1-Shyam-sundar.S-k@amd.com
Signed-off-by: Linus Walleij -
The Toshiba Visconti TMPV7700 series pin controller is only present on
Visconti SoCs. Hence add a dependency on ARCH_VISCONTI, to prevent
asking the user about this driver when configuring a kernel without
Visconti platform support.Fixes: a68a7844264e4fb9 ("pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support")
Signed-off-by: Geert Uytterhoeven
Acked-by: Nobuhiro Iwamatsu
Link: https://lore.kernel.org/r/20201005125049.26926-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij -
The pinctrl driver can work without the EINT resource, but, if it is
expected to have this resource but the mtk_build_eint() function fails
after allocating their data (because can't get the resource or can't map
the irq), the data is not freed and you end with a NULL pointer
dereference. Fix this by freeing the data if mtk_build_eint() fails, so
pinctrl still works and doesn't hang.This is noticeable after commit f97dbf48ca43 ("irqchip/mtk-sysirq: Convert
to a platform driver") on MT8183 because, due this commit, the pinctrl driver
fails to map the irq and spots the following bug:[ 1.947597] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000004
[ 1.956404] Mem abort info:
[ 1.959203] ESR = 0x96000004
[ 1.962259] EC = 0x25: DABT (current EL), IL = 32 bits
[ 1.967565] SET = 0, FnV = 0
[ 1.970613] EA = 0, S1PTW = 0
[ 1.973747] Data abort info:
[ 1.976619] ISV = 0, ISS = 0x00000004
[ 1.980447] CM = 0, WnR = 0
[ 1.983410] [0000000000000004] user address but active_mm is swapper
[ 1.989759] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[ 1.995322] Modules linked in:
[ 1.998371] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc1+ #44
[ 2.004715] Hardware name: MediaTek krane sku176 board (DT)
[ 2.010280] pstate: 60000005 (nZCv daif -PAN -UAO BTYPE=--)
[ 2.015850] pc : mtk_eint_set_debounce+0x48/0x1b8
[ 2.020546] lr : mtk_eint_set_debounce+0x34/0x1b8
[ 2.025239] sp : ffff80001008baa0
[ 2.028544] x29: ffff80001008baa0 x28: ffff0000ff7ff790
[ 2.033847] x27: ffff0000f9ec34b0 x26: ffff0000f9ec3480
[ 2.039150] x25: ffff0000fa576410 x24: ffff0000fa502800
[ 2.044453] x23: 0000000000001388 x22: ffff0000fa635f80
[ 2.049755] x21: 0000000000000008 x20: 0000000000000000
[ 2.055058] x19: 0000000000000071 x18: 0000000000000001
[ 2.060360] x17: 0000000000000000 x16: 0000000000000000
[ 2.065662] x15: ffff0000facc8470 x14: ffffffffffffffff
[ 2.070965] x13: 0000000000000001 x12: 00000000000000c0
[ 2.076267] x11: 0000000000000040 x10: 0000000000000070
[ 2.081569] x9 : ffffaec0063d24d8 x8 : ffff0000fa800270
[ 2.086872] x7 : 0000000000000000 x6 : 0000000000000011
[ 2.092174] x5 : ffff0000fa800248 x4 : ffff0000fa800270
[ 2.097476] x3 : ffff8000100c5000 x2 : 0000000000000000
[ 2.102778] x1 : 0000000000000000 x0 : 0000000000000000
[ 2.108081] Call trace:
[ 2.110520] mtk_eint_set_debounce+0x48/0x1b8
[ 2.114870] mtk_gpio_set_config+0x5c/0x78
[ 2.118958] gpiod_set_config+0x5c/0x78
[ 2.122786] gpiod_set_debounce+0x18/0x28
[ 2.126789] gpio_keys_probe+0x50c/0x910
[ 2.130705] platform_drv_probe+0x54/0xa8
[ 2.134705] really_probe+0xe4/0x3b0
[ 2.138271] driver_probe_device+0x58/0xb8
[ 2.142358] device_driver_attach+0x74/0x80
[ 2.146532] __driver_attach+0x58/0xe0
[ 2.150274] bus_for_each_dev+0x70/0xc0
[ 2.154100] driver_attach+0x24/0x30
[ 2.157666] bus_add_driver+0x14c/0x1f0
[ 2.161493] driver_register+0x64/0x120
[ 2.165319] __platform_driver_register+0x48/0x58
[ 2.170017] gpio_keys_init+0x1c/0x28
[ 2.173672] do_one_initcall+0x54/0x1b4
[ 2.177499] kernel_init_freeable+0x1d0/0x238
[ 2.181848] kernel_init+0x14/0x118
[ 2.185328] ret_from_fork+0x10/0x34
[ 2.188899] Code: a9438ac1 12001266 f94006c3 121e766a (b9400421)
[ 2.194991] ---[ end trace 168cf7b3324b6570 ]---
[ 2.199611] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 2.207260] SMP: stopping secondary CPUs
[ 2.211294] Kernel Offset: 0x2ebff4800000 from 0xffff800010000000
[ 2.217377] PHYS_OFFSET: 0xffffb50500000000
[ 2.221551] CPU features: 0x0240002,2188200c
[ 2.225811] Memory Limit: none
[ 2.228860] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---Fixes: 89132dd8ffd2 ("pinctrl: mediatek: extend eint build to pinctrl-mtk-common-v2.c")
Signed-off-by: Enric Balletbo i Serra
Acked-by: Sean Wang
Link: https://lore.kernel.org/r/20201001142511.3560143-1-enric.balletbo@collabora.com
[rebased on changed infrastructure]
Signed-off-by: Linus Walleij
06 Oct, 2020
4 commits
-
Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the
wakeirqs during suspend entry.Signed-off-by: Maulik Shah
Signed-off-by: Marc Zyngier
Tested-by: Stephen Boyd
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
Acked-by: Linus Walleij
Link: https://lore.kernel.org/r/1601267524-20199-5-git-send-email-mkshah@codeaurora.org -
msmgpio irqchip was not using return value of irq_set_irq_wake() callback
since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor
it implemented .irq_set_wake callback. This lead to irq_set_irq_wake()
return error -ENXIO.However from 'commit 4110b5cbb014 ("irqchip/gic-v3: Allow interrupt to be
configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE
flag.Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent()
instead of always returning success.Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah
Signed-off-by: Marc Zyngier
Tested-by: Stephen Boyd
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
Acked-by: Bjorn Andersson
Acked-by: Linus Walleij
Link: https://lore.kernel.org/r/1601267524-20199-3-git-send-email-mkshah@codeaurora.org -
Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already
set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked
during suspend or during setting irq type since genirq checks irqchip flag
of msmgpio irqchip which forwards these calls to its parent PDC irqchip.Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during
suspend and mask before setting irq type. Masking before changing type make
sures any spurious interrupt is not detected during this operation.Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah
Signed-off-by: Marc Zyngier
Tested-by: Stephen Boyd
Reviewed-by: Douglas Anderson
Acked-by: Bjorn Andersson
Acked-by: Linus Walleij
Link: https://lore.kernel.org/r/1601267524-20199-2-git-send-email-mkshah@codeaurora.org -
Linux 5.9-rc8
Signed-off-by: Greg Kroah-Hartman
Change-Id: I4a03857522443f5d032a0cc1ecdced3675255d5e
01 Oct, 2020
4 commits
-
The debug output in pcs_parse_one_pinctrl_entry() needs to be updated
to print the correct pinctrl register value when #pinctrl-cells is 2.Fixes: a13395418888 ("pinctrl: single: parse #pinctrl-cells = 2")
Reported-by: Trent Piepho
Signed-off-by: Drew Fustini
Acked-by: Tony Lindgren
Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/
Link: https://lore.kernel.org/r/20200913230306.2061645-1-drew@beagleboard.org
Signed-off-by: Linus Walleij -
The property #pinctrl-cells can either be 1 or 2:
- if #pinctrl-cells = , then pinctrl_spec.args_count = 2
- if #pinctrl-cells = , then pinctrl_spec.args_count = 3All other values of pinctrl_spec.args_count are incorrect. This fix
checks the upper bound instead of just the lower bound.Fixes: a13395418888 ("pinctrl: single: parse #pinctrl-cells = 2")
Reported-by: Trent Piepho
Signed-off-by: Drew Fustini
Acked-by: Tony Lindgren
Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/
Link: https://lore.kernel.org/r/20200930174839.1308344-1-drew@beagleboard.org
Signed-off-by: Linus Walleij -
check mtk_is_virt_gpio input parameter,
virtual gpio need to support eint mode.add error handler for the ko case
to fix this boot fail:
pc : mtk_is_virt_gpio+0x20/0x38 [pinctrl_mtk_common_v2]
lr : mtk_gpio_get_direction+0x44/0xb0 [pinctrl_paris]Fixes: edd546465002 ("pinctrl: mediatek: avoid virtual gpio trying to set reg")
Signed-off-by: Hanks Chen
Acked-by: Sean Wang
Singed-off-by: Jie Yang
Link: https://lore.kernel.org/r/1597922546-29633-1-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij -
Correct sdc2_clk pin definition (register offset is wrong, verified by
the msm-4.19 driver).Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.")
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
Acked-by: Manivannan Sadhasivam
Link: https://lore.kernel.org/r/20200914091846.55204-1-dmitry.baryshkov@linaro.org
Signed-off-by: Linus Walleij
