23 Feb, 2017
9 commits
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This patch updates all clk driver from L3.14.y, as
cherry-pick all clk related patch needs to handle
about 40 patches conflicts, so just copy it from
L3.14.y as it is an independent driver, for commit
log, please refer to L3.14.y.Signed-off-by: Anson Huang
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Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:&clks {
assigned-clocks = ,
;
assigned-clock-parents = ,
;
};The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf
Signed-off-by: Ranjani Vaidyanathan
Signed-off-by: Fabio Estevam
Signed-off-by: Philipp Zabel
Reviewed-by: Akshay Bhat
Tested-by Joshua Clayton
Tested-by: Charles Kang
Signed-off-by: Shawn Guo -
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. As this can not be guaranteed by
the clock framework during runtime, make the ldb_di[x]_sel muxes read-only.
A workaround to set the muxes once during boot could be added to the
kernel or bootloader.Signed-off-by: Philipp Zabel
Signed-off-by: Fabio Estevam
Signed-off-by: Shawn Guo -
MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the
parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never
succeed.
Disable the handshake mechanism to allow changing the frequency of
mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI
clock.Signed-off-by: Philipp Zabel
Signed-off-by: Fabio Estevam
Signed-off-by: Shawn Guo -
Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.Signed-off-by: Anson Huang
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* Fix PLL Audio/Video Numerator/Denominator register offsets
* In imx7d pll register CCM_ANALOG_PLL_VIDEO_NUM and
CCM_ANALOG_PLL_VIDEO_DENOM offset is different with imx6.
For imx7D the correct setting should be:
PLL_NUM_OFFSET 0x20
PLL_DENOM_OFFSET 0x30
* Add additional macros to handle imx7d audio/video
pll num/demom offset settings.Signed-off-by: Adrian Alonso
[Octavian: use IMX_PLLV3_AV_IMX7 instead of cpu_is_imx7d()]
Signed-off-by: Octavian Purdila -
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.There is a test_div placed before DRAM PLL's gate, so
add this test div clk.Signed-off-by: Anson Huang
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Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
which is the output of USBOTG2 PHY.Signed-off-by: Peter Chen
(cherry picked from commit 5abb3c7e2ce78dcf5d37e5435abed992841d63f2) -
enable rpmsg on imx amp platforms
- use MU receive interrupter as the notify of the multi-cores.
- add the MU root clock support on imx7dSigned-off-by: Richard Zhu
[Octavian: select VIRTIO_RPMGS, fix for VIRTIO_RPMSG_F_NS removal]
Signed-off-by: Octavian Purdila
15 Jan, 2017
1 commit
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commit 9388093db44356af911adf3d355b7544a13a63cd upstream.
Unlike clk_register_clkdev(), clk_hw_register_clkdev() doesn't check for
passed error objects from a previous registration call. Hence the caller
of clk_hw_register_*() has to check for errors before calling
clk_hw_register_clkdev*().Make clk_hw_register_clkdev() more similar to clk_register_clkdev() by
adding this error check, removing the burden from callers that do mass
registration.Fixes: e4f1b49bda6d6aa2 ("clkdev: Add clk_hw based registration APIs")
Fixes: 944b9a41e004534f ("clk: ls1x: Migrate to clk_hw based OF and registration APIs")
Fixes: 44ce9a9ae977736f ("MIPS: TXx9: Convert to Common Clock Framework")
Fixes: f48d947a162dfa9d ("clk: clps711x: Migrate to clk_hw based OF and registration APIs")
Fixes: b4626a7f489238a5 ("CLK: Add Loongson1C clock support")
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Russell King
Signed-off-by: Greg Kroah-Hartman
12 Jan, 2017
8 commits
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commit e2a33c34ddff22ee208d80abdd12b88a98d6cb60 upstream.
The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Tested-by: Geert Uytterhoeven
Acked-by: Kuninori Morimoto
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
commit bae203d58b7dce89664071b3fafe20cedaa3e4f6 upstream.
Function mx31_clocks_init() is called during clock intialization on
legacy boards with reference clock frequency passed as its input
argument, this can be verified by examination of the function
declaration found in arch/arm/mach-imx/common.h and actual function
users which include that header file.Inside CCF driver the function ignores its input argument, by chance
the used value in the function body is the same as input arguments on
side of all callers.Fixes: d9388c843237 ("clk: imx31: Do not call mxc_timer_init twice when booting with DT")
Signed-off-by: Vladimir Zapolskiy
Reviewed-by: Uwe Kleine-König
Acked-by: Stephen Boyd
Signed-off-by: Shawn Guo
Signed-off-by: Greg Kroah-Hartman -
commit 0f6f9302b819ca352cfd4f42c18ec08d521f9cae upstream.
The audio module clocks are supposed to be set according to the sample
rate of the audio stream. The audio PLL provides the clock signal for
these module clocks, and only it is freely tunable.Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
properly tune the clock rate.Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
Signed-off-by: Greg Kroah-Hartman -
commit 937ff9ded8b6ebe8963ade55bdd77a61ded88075 upstream.
The audio module clocks are supposed to be set according to the sample
rate of the audio stream. The audio PLL provides the clock signal for
these module clocks, and only it is freely tunable.Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
properly tune the clock rate.Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
Signed-off-by: Greg Kroah-Hartman -
commit f8d17344a60921c2387759fc0a85aa64299d1ec6 upstream.
Prevent creating clk alias for non existing gmac_gmii_ref_clk_div clock and,
this way, eliminate excessive error message during boot:"ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div"
Fixes: c097338ebd3f ("ARM: dts: dra7: cpsw: fix clocks tree")
Signed-off-by: Grygorii Strashko
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
commit 20979202ee6e4c68dab7bcf408787225a656d18e upstream.
Fix bug https://bugzilla.kernel.org/show_bug.cgi?id=188561. Function
wm831x_clkout_is_prepared() returns "true" when it fails to read
CLOCK_CONTROL_1. "true" means the device is already prepared. So
return "true" on the read failure seems improper.Signed-off-by: Pan Bian
Acked-by: Charles Keepax
Fixes: f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
commit cbf2e548ca8ad4bb274d014e9a70bd841d29948e upstream.
The clocks on these boards run at 25 MHz, not 19.2 and 27 like
other platforms. Unfortunately I copy/pasted from other similar
SoCs but forgot this one is different. Fix it.Fixes: a085f877a882 ("clk: qcom: Move cxo/pxo/xo into dt files")
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
commit bc4725d9029e2c8205fbaf1105e193d1c4e463bb upstream.
The intention was to enable the checks if debugging is enabled, not
disabled.Fixes: f793d1e51705b276 ("clk: shmobile: Add new CPG/MSSR driver core")
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Greg Kroah-Hartman
09 Jan, 2017
1 commit
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commit 68af4fa8f39b542a6cde7ac19518d88e9b3099dc upstream.
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.Signed-off-by: Boris Brezillon
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Reviewed-by: Eric Anholt
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman
06 Jan, 2017
1 commit
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commit 035cd485a47dda64f25ccf8a90b11a07d0b7aa7a upstream.
The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term
frequency drift. The frequency drift magnitude depends on the VCO update
rate, which is inversely proportional to the PLL divider. The kernel
DPLL configuration code results in a high value for the divider, leading
to a long term drift high enough to cause USB transmission errors. In
the worst case the USB PHY's ULPI interface can stop responding,
breaking USB operation completely. This manifests itself on the
Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the
cable is bad?' in the kernel log.Errata sprz319 advisory 2.1 documents PLL values that minimize the
drift. Use them automatically when DPLL5 is used for USB operation,
which we detect based on the requested clock rate. The clock framework
will still compute the PLL parameters and resulting rate as usual, but
the PLL M and N values will then be overridden. This can result in the
effective clock rate being slightly different than the rate cached by
the clock framework, but won't cause any adverse effect to USB
operation.Signed-off-by: Richard Watts
[Upported from v3.2 to v4.9]
Signed-off-by: Laurent Pinchart
Tested-by: Ladislav Michl
Signed-off-by: Stephen Boyd
Cc: Adam Ford
Signed-off-by: Greg Kroah-Hartman
01 Dec, 2016
1 commit
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Pull clk fixes from Stephen Boyd:
"Two small fixes for MIPI PLLs on sunxi devices and a build fix for a
Broadcom clk driver having unmet dependencies"* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX
clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it
24 Nov, 2016
2 commits
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With commit f4e871509959 ("clk: iproc: Make clocks visible options"),
COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX
also selects that option, this causes the following Kconfig warning:warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct
dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) && COMMON_CLK)Fix this by adding proper depends for COMMON_CLK_IPROC
Fixes: f4e871509959 ("clk: iproc: Make clocks visible options")
Signed-off-by: Florian Fainelli
Reviewed-by: Ray Jui
[sboyd@codeaurora.org: Drop default part as it's redundant]
Signed-off-by: Stephen Boyd -
In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control
register is called "LDO{1,2}_EN", and according to the BSP source code
from Allwinner [1], the LDOs are enabled during the clock's enabling
process.The clock failed to generate output if the two LDOs are not enabled.
Add the two bits to the clock's gate bits, so that the LDOs are enabled
when the PLL is enabled.[1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429
Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
22 Nov, 2016
1 commit
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The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.Add the 2 LDO enable bits to the gate bits. This fixes issues with
the TCON not sending vblank interrupts when the tcon and dot clock are
indirectly clocked from the PLL-MIPI clock.Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
17 Nov, 2016
3 commits
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…el/git/mripard/linux into clk-fixes
Pull Allwinner clock fixes from Maxime Ripard:
Two fixes, one for the old clock code, one for the new implementation.
* tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi: Fix M factor computation for APB1
clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent -
Dan Carpenter reports that we're passing a pointer to a pointer
here when we should just be passing a pointer. Pass the right
pointer so that the of_clk_hw_onecell_get() sees the appropriate
data pointer on its end.Reported-by: Dan Carpenter
Cc: Stephen Boyd
Cc: Uwe Kleine-König
Fixes: 9337631f52a8 ("clk: efm32gg: Migrate to clk_hw based OF and registration APIs")
Signed-off-by: Stephen Boyd -
Dan Carpenter reports that we're passing a pointer to a pointer
here when we should just be passing a pointer. Pass the right
pointer so that the of_clk_hw_onecell_get() sees the appropriate
data pointer on its end.Reported-by: Dan Carpenter
Cc: Jisheng Zhang
Cc: Alexandre Belloni
Cc: Sebastian Hesselbarth
Cc: Stephen Boyd
Fixes: f6475e298297 ("clk: berlin: Migrate to clk_hw based registration and OF APIs")
Signed-off-by: Stephen Boyd
04 Nov, 2016
1 commit
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commit cfa636886033 ("clk: sunxi: factors: Consolidate get_factors
parameters into a struct") introduced a regression for m factor
computation in sun4i_get_apb1_factors function.The old code reassigned the "parent_rate" parameter to the targeted
divisor value and was buggy for the returned frequency but not for the
computed factors. Now, returned frequency is good but m factor is
incorrectly computed (its max value 31 is always set resulting in a
significantly slower frequency than the requested one...)This patch simply restores the original proper computation for m while
keeping the good changes for returned rate.Fixes: cfa636886033 ("clk: sunxi: factors: Consolidate get_factors parameters into a struct")
Signed-off-by: Stéphan Rafin
Signed-off-by: Maxime Ripard
02 Nov, 2016
6 commits
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Fix the retrn value check which testing the wrong variable
in pxa910_clk_init().Fixes: 2bc61da9f7ff ("clk: mmp: add pxa910 DT support for clock driver")
Signed-off-by: Wei Yongjun
Signed-off-by: Stephen Boyd -
Fix the retrn value check which testing the wrong variable
in pxa168_clk_init().Fixes: ab08aefcd12d ("clk: mmp: add pxa168 DT support for clock driver")
Signed-off-by: Wei Yongjun
Signed-off-by: Stephen Boyd -
Fix the retrn value check which testing the wrong variable
in mmp2_clk_init().Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver")
Signed-off-by: Wei Yongjun
Signed-off-by: Stephen Boyd -
The boot-time frequency of a CPU is considered its rated maximum, as we
have no other source of such information. However, this was previously
only used for chips with 80% restrictions on secondary PLLs. This
usually wasn't a problem because most chips/configs boot with a divider
of /1, with other dividers being used only for dynamic frequency
reduction. However, at least one config (LS1021A at less than 1 GHz)
uses a different divider for top speed. This was causing cpufreq to set
a frequency beyond the chip's rated speed.This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs,
similar to the existing 80% limit that only applied to some.Signed-off-by: Scott Wood
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd -
…/git/mmind/linux-rockchip into clk-fixes
Fix return value in error case of new ddrclk type.
* tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: don't return NULL when failing to register ddrclk branch -
Since 'parent_rate * mfn' may overflow 32 bits, the result should be
stored using 64 bits.The problem was discovered when trying to set the rate of the audio PLL
(pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but
the actual rate returned was 192.000570 MHz. The round rate function should
have been able to return 196.608 MHz, i.e., the desired rate.Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula")
Cc: Anson Huang
Signed-off-by: Emil Lundmark
Reviewed-by: Fabio Estevam
Acked-by: Shawn Guo
Signed-off-by: Stephen Boyd
29 Oct, 2016
1 commit
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ioremaped addresses are not linearly mapped so the physical
address can not be figured out via __pa. More generally, there
is no guarantee that backing value of an ioremapped address
is a physical address at all. The value here is only used
for debugging so just drop the call to __pa on the ioremapped
address.Fixes: 6ae5fd381251 ("clk: xgene: Silence sparse warnings")
Signed-off-by: Laura Abbott
Acked-by: Loc Ho
Signed-off-by: Stephen Boyd
28 Oct, 2016
1 commit
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The Exynos PMU node is an interrupt, clock and PMU (Power Management Unit)
controller, and these functionalities are supported by different drivers
that matches the same compatible strings.Since commit 989eafd0b609 ("clk: core: Avoid double initialization of
clocks") the OF core flags clock controllers registered with the
CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same
compatible string will not be registered.This prevents the PMU platform device to be created, so the Exynos PMU
driver is never probed. This breaks (among other things) Suspend-to-RAM.Fix this by changing CLKOUT driver initialization method to
CLK_OF_DECLARE_DRIVER(), which doesn't clear the OF_POPULATED flag, so
later a platform device is created and the Exynos PMU platform driver
can be be probed properly.Fixes: 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
Signed-off-by: Marek Szyprowski
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Chanwoo Choi
Signed-off-by: Stephen Boyd
21 Oct, 2016
1 commit
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If 'clk_hw_register()' fails, it is likely that we expect to return an
error instead of a valid pointer (which would mean success).Fix commit f5644f10dcfb ("clk: at91: Migrate to clk_hw based registration
and OF APIs")Signed-off-by: Christophe JAILLET
Signed-off-by: Stephen Boyd
20 Oct, 2016
2 commits
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I made a mistake as for naming for this block. The MIO block is not
implemented for these 3 SoCs in the first place. The current naming
will be a trouble if an SoC with both MIO and SD-ctrl blocks appear
in the future.This driver has just been merged in the previous merge window.
Rename it before the release.Signed-off-by: Masahiro Yamada
Signed-off-by: Stephen Boyd -
The first loop of this "for" statement writes memory beyond the
allocated clk_hw_onecell_data.It should be:
for (clk_num--; clk_num >= 0; clk_num--)
...Or more simply:
while (--clk_num >= 0)
...Fixes: 734d82f4a678 ("clk: uniphier: add core support code for UniPhier clock driver")
Signed-off-by: Masahiro Yamada
Signed-off-by: Stephen Boyd
19 Oct, 2016
1 commit
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On the A31, the DMA engine only works if AHB1 is clocked from PLL6.
In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked
from the CPU clock, and cpufreq is working, we get an unstable timer.Force the AHB1 clock to use PLL6 as its parent. Previously this was done
in the device tree with the assigned-clocks and assigned-clocks-parent
bindings. However with this new monolithic driver, the system critical
clocks aren't exported through the device tree. The alternative is to
force this setting in the driver before the clocks are registered.This is also done in newer versions of mainline U-boot. But people still
using an older version, or even the vendor version, can still hit this
issue. Hence the need to do it in the kernel as well.Reported-by: Hans de Goede
Reported-by: Maxime Ripard
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard