04 Apr, 2017

1 commit

• 3071f13d7   perf: qcom: Add L3 cache PMU driver ... Browse Code »

  This adds a new dynamic PMU to the Perf Events framework to program
  and control the L3 cache PMUs in some Qualcomm Technologies SOCs.

  The driver supports a distributed cache architecture where the overall
  cache for a socket is comprised of multiple slices each with its own PMU.
  Access to each individual PMU is provided even though all CPUs share all
  the slices. User space needs to aggregate to individual counts to provide
  a global picture.

  The driver exports formatting and event information to sysfs so it can
  be used by the perf user space tools with the syntaxes:
  perf stat -a -e l3cache_0_0/read-miss/
  perf stat -a -e l3cache_0_0/event=0x21/

  Acked-by: Mark Rutland
  Signed-off-by: Agustin Vega-Frias
  [will: fixed sparse issues]
  Signed-off-by: Will Deacon

  Agustin Vega-Frias

  2017-04-04 01:53:50 +0800  

09 Feb, 2017

1 commit

• 21bdbb710   perf: add qcom l2 cache perf events driver ... Browse Code »

  Adds perf events support for L2 cache PMU.

  The L2 cache PMU driver is named 'l2cache_0' and can be used
  with perf events to profile L2 events such as cache hits
  and misses on Qualcomm Technologies processors.

  Reviewed-by: Mark Rutland
  Signed-off-by: Neil Leeder
  [will: minimise nesting in l2_cache_associate_cpu_with_cluster]
  [will: use kstrtoul for unsigned long, remove redunant .owner setting]
  Signed-off-by: Will Deacon

  Neil Leeder

  2017-02-09 03:32:24 +0800  

16 Sep, 2016

1 commit

• 832c927d1   perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver ... Browse Code »

  This patch adds a driver for the SoC-wide (AKA uncore) PMU hardware
  found in APM X-Gene SoCs.

  Signed-off-by: Tai Nguyen
  Reviewed-by: Mark Rutland

  Tai Nguyen

  2016-09-16 02:20:55 +0800