29 Oct, 2018
40 commits
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Register offset needs to be applied on mapbase also.
dma_tx/rx_request use the physical address of UARTDATA.
Register offset is currently only applied to membase (the
corresponding virtual addr) but not on mapbase.Reviewed-by: Leonard Crestez
Acked-by: Fugang Duan
Signed-off-by: Adriana Reus -
It is better to clear wakeup flag in status register before enable
wakeup interrupt bits, which can avoid system suspend fail during
devices no irq suspend stage.Reviewed-by: Gao Pan
Signed-off-by: Fugang Duan -
i.MX7ULP enter VLLS mode that lpuart module power off and registers
all lost no matter the port is wakeup source.For console port, console baud rate setting lost and print messy
log when enable the console port as wakeup source. To avoid the
issue happen, user should not enable uart port as wakeup source
in VLLS mode, or restore console setting.The patch is to add one fixup to restore console port register setting
for i.MX7ULP platform.Reviewed-by: Gao Pan
Signed-off-by: Fugang Duan -
1) Add code comments for the algorithm idea
2) code cleanups
3) Give a warn one find unacceptable baud rate difference of more
than 3%No function level change.
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng -
If "baud_diff == 0", it means we already found the exact matching baud
rate and no need try looping the left possible baud rates anymore.So in this patch, we break out immediately once we find the right baud
rate to avoid the left meaningless loops.Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng -
This part of code is derived from Kinetis and is obviously invalid for ULP,
So delete it to avoid confusing.Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng -
The driver save/restore registers in system suspend/resume noirq stage
to support no_console_suspend in power lost case.In noirq stage with no_console_suspend, .imx_console_write() _maybe_
called to print out log_buf message in .printk() or console_unlock()
called by other drivers.
It should add port.lock to protect the registers save/restore in noirq
stage since .imx_console_write() also access them.Reported-by: Anson Huang
Signed-off-by: Fugang Duan -
No need to wait dma_wait event, directly terminate rx dma chans
in .shutdown() callback.Signed-off-by: Fugang Duan
Signed-off-by: Robin Gong
Reviewed-by: Robin Gong -
Add runtime pm support to manage lpuart clock and its power domain
to save power in system idle and system suspend stages.Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
Current driver suppose system disable irq when wakeup is not enabled
like below follow, so it always enable the wakeup interrupt in .suspend_noirq().
dpm_suspend_noirq()
device_wakeup_arm_wake_irqs()
if (device_may_wakeup(wirq->dev))
enable_irq_wake(wirq->irq);
irq_set_irq_wake(irq, 1);
suspend_device_irqs();
if (irqd_is_wakeup_set(&desc->irq_data))
__disable_irq(desc);
device_suspend_noirq(dev);
...But in i.MX8x chips, the gic-v3 chip->irq_disable() is not implemented,
so the device's irq line is not masked in noirq stage. Then lpuart interrupt
can wake up system even if it is not enabled as wakeup source.To avoid the issue, only enable wakeup interrupt when it is enabled as
wakeup source.Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
The LOOP mode remained always set after first use.
If the ioctl tiocmset gets called with TIOCMBIC for TIOCM_LOOP,
UARTCTRL_LOOPS needs to be cleared in the LPUART control register.Signed-off-by: Abel Vesa
Acked-by: Fugang Duan -
Although .startup() alreadly do transmit/receive fifo/buffer flush,
but switch the baud rate may introduce dirty data on fifo, in such
case, user will call tcflush() to clean up buffer and fifo. So driver
also ensure HW fifo is cleaned up.The patch add hw fifo/buffer flush in .flush_buffer() callback.
Signed-off-by: Fugang Duan
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Add busfreq support for DMA mode.
Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
Ensure ipg clock enable during .uart_resume_port() that call set
ops->set_mctrl() before ops->startup().BuildInfo:
- SCFW daf9431c, IMX-MKIMAGE 1c6fc7d8, ATF f2547fb
- U-Boot 2017.03-00097-gd7599cfSigned-off-by: Fugang Duan
Reviewed-by: Robin Gong -
Keep per clock disabled during system suspend.
BuildInfo:
- SCFW 88456c73, IMX-MKIMAGE 06bc2767, ATF a438801
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g7953d47Signed-off-by: Fugang Duan
Reviewed-by: Anson Huang -
The dmaengine_prep_slave_sg needs to use sg count returned
by dma_map_sg, not use sport->dma_tx_nents, because the return
value of dma_map_sg is not always same with "nents".When enabling iommu for lpuart + edma, iommu framework may concatenate
two sgs into one.Fixes: 6250cc30c4c4e ("tty: serial: fsl_lpuart: Use scatter/gather DMA for Tx")
Signed-off-by: Peng Fan
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In DMA EEOP mode idle flag can trigger DMA major loop stop. The idle
flag should be cleared by HW. So others cannot clear idle flag in the
mode enabled.Signed-off-by: Fugang Duan
Reviewed-by: Pandy Gao -
Add port.lock to protect register accessing in suspend/resume function.
Disable RIE and ILIE before DMA chan is ternminated in suspend function.Signed-off-by: Fugang Duan
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When use lpuart with DMA mode as wake up source, it still switch to
cpu mode in .suspend() that enable cpu interrupts RIE and ILIE as
wakkup source. When the wakeup signal coming while rx dma chan is
already teminated down, then driver should not call irq handler to
submit the new dma descriptor.Enable the wakeup irq bits in .suspend_noirq() and disable the wakeup
irq bits in .resume_noirq().Signed-off-by: Fugang Duan
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There have a corner case that tx DMA .callback() is comming after
.flush_buffer(), then .callback() should check dma_tx_in_progress
flag and return in directly.Signed-off-by: Fugang Duan
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In below case:
write() -> flush() -> write() -> flush() ....imx_flush_buffer() _MAY_ clear UCR1_TDMAEN bit if the callback is not
comming or DMA transfer is not completed, to ensure DMA trigger is enabled
for the new DMA prep_sg, enable the UCR1_TDMAEN bit in .dma_tx_work().Signed-off-by: Fugang Duan
Tested-by: Fabio Estevam
Tested-by: David Wolfe -
In DMA tx callback, .uart_circ_chars_pending() also should be protected
by the port.lock, and in DMA rx callback, it can remove the lock protection
for .lpuart_copy_rx_to_tty() and .tty_flip_buffer_push() code range.Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong
Reviewed-by: Dong Aisheng -
Add port.icount to stat. the DMA RX received count.
Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
For lpuart32 loopback mode, DMA transfer length should be litter
than the tx/rx fifo free size to ensure there have no overrun.Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
imx8qm lpuart support dma eeop:
- rx fifo > watermark level: watermark level RDRF triggler
- rx fifo
Reviewed-by: Robin Gong -
After set the new baud rate, wait some time for the stable.
Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
Fix the typo in ipg clock get failed path.
Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
Free the rx dma buffer when the port is closed.
Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
Since the driver stats the error frames in port.icount.frame, it can
drop the error frame that no need to push it to the tty buffer.Signed-off-by: Fugang Duan
Reviewed-by: Robin Gong -
lpuart only use NXP/FSL eDMA dmaengine in i.MX/Vybrid/LS1021a platform,
and eDMA driver don't reuse descriptor then no need to check the
flag DMA_CTRL_ACK. And current eDMA driver use virt chan mechanism and
free tx_descriptor memory after .callback(), but .lpuart_timer_func()
first to terminate the chans that free the tx_descriptor memory, then
access the tx->flags, which cause kmem_cache_alloc() failed to allocate
the freed memory. So remove the unnecessary .async_tx_ack().Signed-off-by: Fugang Duan
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Otherwise there are warning when remove COMPILE_TEST
Signed-off-by: Frank Li
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By default, .of_dma_configure() init dev.coherent_dma_mask to BIT(32) that
match the eDMA address range. If re-init dev.coherent_dma_mask to zero, then
streaming dma mapping will go swiotlb dma_map, if swiotlb is not initalized
then it causes mapping failed.Signed-off-by: Fugang Duan
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The current driver don't support lpuart32 DMA mode.
The patch add lpuart32 tx/rx DMA support, there have two main changes:
- lpuart32 tx dma resue lpuart tx dma mode to reduce code duplication.
- lpuart32 rx dma still use prep_sg mode since imx7ulp don't support
eeop mode that also ailgned with 4.1.y.If don't use DMA mode, remove dma chan property in dts file.
Signed-off-by: Fugang Duan
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i.MX8QM lpuart has ipg_clk and per_clk, ipg_clk for bus and register
accessing, per_clk is lpuart module clock. Add per_clk support in
driver.Signed-off-by: Fugang Duan
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tty_port flag "ASYNC_SUSPENDED" has been discarded from kernel upgrade, then
use .tty_port_suspended() instead of the flag check.Signed-off-by: Fugang Duan
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Add modem device reset, wthether to reset depend on dts configuration.
Signed-off-by: Fugang Duan
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Pass ->dev to dma_alloc_coherent() API to avoid kernel dump.
Signed-off-by: Fugang Duan
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Before then DMA tx path, init the DMA tx path synchronal flags
sport->flags.Signed-off-by: Fugang Duan
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Only enable RTSD interrupt for hw flow control, otherwise RTS_B signal
has some external signal disturbance without config RTS_B select input.Signed-off-by: Fugang Duan
(cherry picked from commit: 471e8c43aca3)Conflicts:
drivers/tty/serial/imx.c -
Add dma memory check before free it.
Signed-off-by: Fugang Duan