23 Feb, 2017
35 commits
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This patch adds missing parentheses around the argument of the macro
WROD to avoid any potential macro expansion issue.Signed-off-by: Liu Ying
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This patch adds missing parentheses around the arguments of the macro
ipu_ch_param_addr/ipu_ch_param_set_field(_io)/ipu_ch_param_mod_field(_io)/
ipu_ch_param_read_field(_io) to avoid any potential macro expansion issue.Signed-off-by: Liu Ying
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This patch adds missing parentheses around the argument of the macro
idma_is_valid and idma_mask to avoid any potential macro expansion issue.Signed-off-by: Liu Ying
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The local variable div_ratio could be less than zero, so let's define
it as type of int32_t instead of uint32_t.This issue is reported by Coverity:
Unsigned compared against 0 (NO_EFFECT)
unsigned_compare: This less-than-zero comparison of an unsigned value
is never true. div_ratio < 0U.
if (div_ratio > 0xFF || div_ratio < 0) {
dev_dbg(ipu->dev, "value of pixel_clk extends normal range\n");
return -EINVAL;
}Signed-off-by: Liu Ying
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This patch converts macro tri_cur_buf_mask/shift to function to address the
following issue reported by Coverity:
Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
result_independent_of_operands: dma_chan * 2 != 63 is always true regardless of
the values of its operands. This occurs as the logical first operand of '?:'.Signed-off-by: Liu Ying
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A minor improvement for _ipu_is_smfc_chan() to address the following
issue reported by Coverity:
Unsigned compared against 0 (NO_EFFECT)
unsigned_compare: This greater-than-or-equal-to-zero comparison of an
unsigned value is always true. dma_chan >= 0U.
return ((dma_chan >= 0) && (dma_chan -
This patch fixes the following issue reported by Coverity:
if (IS_ERR(clk))
freed_arg: kfree frees clk. [Note: The source code implementation of the
function has been overridden by a builtin model.]
kfree(clk);Use after free (USE_AFTER_FREE)
use_after_free: Using freed pointer clk.
return clk;Signed-off-by: Liu Ying
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This patch fixes the following issue reported by Coverity:
if (IS_ERR(clk))
freed_arg: kfree frees clk. [Note: The source code implementation of the
function has been overridden by a builtin model.]
kfree(clk);Use after free (USE_AFTER_FREE)
use_after_free: Using freed pointer clk.
return clk;Signed-off-by: Liu Ying
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This patch fixes the following issue reported by Coverity:
Constant expression result (CONSTANT_EXPRESSION_RESULT)
always_true_or: The "or" condition disp != 0 || disp != 1 will always be true
because disp cannot be equal to two different values at the same time, so it
must be not equal to at least one of them.
if ((disp != 0) || (disp != 1))
return;Signed-off-by: Liu Ying
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We should do the bailout dance correctly for the ioctrl IPU_ALLOC:
- Free the mem pointer.
- Free the DMA.
- Delete the mem->list from the ipu_alloc_list.The potential memory leakage issue on the mem pointer is reported by Coverity:
if (get_user(size, argp))
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable mem going out of scope leaks the storage it points to.
return -EFAULT;Signed-off-by: Liu Ying
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The pre_list can be accessed in an irq context. To avoid potential hang up
issue, use spinlock to protect pre_list instead of mutex.Signed-off-by: Liu Ying
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Currently 128M reserved for GPU in all the i.MX6 boards that is
requiring kernel to allocate CMA 320M. For the low end devices like 6SX
and 6SL, the 320M is huge. Sometimes customer board may have very less
RAM.With Kernel 4.1, there is a new feature CMA can be calculated at DTS
level based on the amount queried from different module drivers.So
moving the GPU memory to DTS is valid and can be configured for each
board.And at the same time, also keep the option for user to configure the
parameters "contiguousBase and contiguousSize" in u-boot.Signed-off-by: Shawn Xiao
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sim_activate() process is contained in the cold reset.
Thus, it is redundant and should be removed.This patch also adds comments to cold reset process.
Signed-off-by: Gao Pan
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In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.In non-small y resolution cases(>9 lines), we choose to check the STORE_BLOCK_Y
field of the register HW_PRE_STRORE_ENGINE_STATUS to determine the bad window
to update the SDW_UDPATE bit of the PRE_CTRL register. According to the
description of the STRORE_BLOCK_Y field in block mode, the field indicates the
Y coordinate of the block currently being rendered. Thus, we should round up
the real display y resolution to 4 lines to align with the block high(the out-
standing lines are cropped by PRG and IPU). To maximize the safe window, we
just need to avoid updating the shadow bit during the last block of lines.
To conclude, the bad window for block mode is (store_block_y == 0 ||
store_block_y >= DIV_ROUND_UP(y_resolution, 4) - 1).Signed-off-by: Liu Ying
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In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.The software mechanism to set the PRE_CTRL register is different for PRE Y
resolution higher than 9 lines and lower than or equal to 9 lines.For cases in which Y resolution is higher than 9 lines, before we update PRE
shadow, we just need to wait until the PRE store engine status runs out of
the problematic PRE automatic writing window.While for cases in which Y resolutin is lower than or equal to 9 lines, we
have to update PRE shadow in the buffer flip interrupt handler.Signed-off-by: Liu Ying
(cherry picked from commit bd9c14e24aaf67926dfd31bd819ab0c87129fe4b) -
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.This patch exports a function to set the PRE_CTRL register so that it could be
used by the software when the PRE automatic writing doesn't happen for sure.Signed-off-by: Liu Ying
(cherry picked from commit e64bbcd9243a17f9eba9cb3abb6f2c1939eae110) -
LVDS0 can not work on imx6q auto and SDB board,
it is caused by ldb0 clock setting is missed in ipu driver.Signed-off-by: Sandor Yu
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i.MX6SX has MLB150, add support for it.
Signed-off-by: Anson Huang
(cherry picked from commit 99d374da7d49d45800821b28d55e032387f1cc67) -
GPU is NOT just depending on i.MX6Q, enable it for all i.MX6 SOCs.
Signed-off-by: Anson Huang
(cherry picked from commit 06b8da5c28dc2fec0160bc60cc846d4910a05b41) -
MIPI_CSI2 is necessary for modules build, enable it for all
i.MX6 and i.MX7 SOC.Signed-off-by: Anson Huang
(cherry picked from commit 2e2025df741a79620be9b96fa6fb0f2e2e40fdea) -
Fix buiulding warning:
drivers/mxc/ipu3/ipu_disp.c:435:29: warning: initialization discards
'const' qualifier from pointer target type
[-Wdiscarded-array-qualifiers]
{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0},
{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG,
&rgb2ycbcr_coeff} },Signed-off-by: Sandor Yu
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4.1 kernel apply the followed patch:
commit 73e0e496afdac9a5190eb3b9c51fdfebcc14ebd4
clkdev: Always allocate a struct clk and call __clk_get() w/ CCFclock_get will return a new struct clk, so we can't use the pointer
of clk struct to compare clk whether is equal, replace with clk name.Signed-off-by: Sandor Yu
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Initial port of the mxc V4L2 capture driver.
Baseline copied from imx_3.14.y branch:Signed-off-by: Sandor Yu
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Fixed wrong symbols of GPU in mxc/Makefile.
Date Sep 22, 2015
Signed-off-by: Shawn Xiao
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1. Upstream 5.0.11p7 driver to kernel
2. Add the GPU configuration to imx6q.dtsi
3. Remove IRQF_DISABLED in GPU driver
The IRQF_DISABLED has been removed from 4.1.0 kernel. To accomodate with
the change, add version check logic and use 0x0 instead of IRQF_DISABLED
from 4.1.0 kernel on.4. Convert file->f_dentry->d_inode to file_inode() in GPU driver
The file struct has changed since 3.19. Changed the usage in GPU driver
too.5. Add version check for CONFIG_PM_RUNTIME
The CONFIG_PM_RUNTIME will never be used in 4.1.0 kernel. Add version
check to avoid calling it in GPU driver.Signed-off-by: Shawn Xiao
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Forward imx_3.14.y IPU and display drivers to 4.1 kernel.
This includes IPU core driver, display driver, LDB and HDMI driver.Signed-off-by: Sandor Yu
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Add mlb support on imx_4.1.y. The files are copied from imx_3.14.y.
Signed-off-by: Gao Pan
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Include 3.14 VPU driver with no change
Signed-off-by: Hongzhang Yang
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The API devm_request_and_ioremap meets compile error
on branch imx_4.1.y. It is recommend to replace the api
with devm_ioremap_resource.Signed-off-by: Gao Pan
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Add the option to enable SIM driver build.
Signed-off-by: Luwei Zhou
Signed-off-by: Gao Pan
(cherry picked from 0f7a6fa3c141bfc7333d9056639b7a5b1154ed1d) -
The EMV4.3 has strict requirement about the reset sequence. The old code use the mdelay, udelay to
achievet, which is not precise enough. Replace it with the timer interrupt. The EMV4.3 requires
40000~45000 clock cycles duration when reset is low.Signed-off-by: Luwei Zhou
(cherry picked from a006fe283c8b97f0a711cb0829bfbdaaf4a5f31f) -
In EMV4.3 after warm/cold reset, there would be a receiving window. The receiving
window would be 42000 clock length.If the receiving window expires without receiving
one byte, IFD need to take actions as EMV4.3 spec. The driver need to support this
to identify the sequence of the receiving window expiring event and the receiving event.
Since theinterrupt latency in linux OS is not certain, we need to tune this setting to
pass the cases. Current tuning parameter can work.Signed-off-by: Luwei Zhou
(cherry picked from faf1d8d881a6ad2c6b88fdf312cef142996937c1) -
The CWT timer is used to detect the the character interval in the data traffic.
When tx, SIM IP can guarantee the interval based our setting. When RX, we need
to enalbe the CWT timer to check whether the interval is in the range. This patch
fix this.Signed-off-by: Luwei Zhou
(cherry picked from 9c92dfd070e7427eb1e0166f368b89b4a7ac1bff) -
Modify the driver to support the SIM on i.MX6UL-EVK platform. The main modification is:
1. Add port index to support different port on platform.
2. Add POS-CARD support. The POS card has external IC to assert when SVEN to low. Add support.
3. Using a function to calculate the strict timing delay.Signed-off-by: Luwei Zhou
(cherry picked from 17d1315b0704e2db63ee6bd7aaefa0c796f53104) -
This driver is based on the current code which runs the the EMV test on the i.MX258 platform.
Since there are still many cases that can't pass on the i.MX258 and i.MX7d platform. The
driver will need to be improved after per-test work. Just check in as a base code. There
would be definitly some timing improvement work to do in the future.Signed-off-by: Luwei Zhou
(cherry picked from 3ac1ad5b2a68ecb052ccacca4ac7459ead04415e)
