28 Aug, 2017
40 commits
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This gave us more freedom to change/add/remove operations without
recompiling all device driver.Typically, Carrier board implement the fmc operations, so they will not
use these helpers.Signed-off-by: Federico Vaga
Tested-by: Pat Riehecky
Acked-by: Alessandro Rubini
Signed-off-by: Greg Kroah-Hartman -
Signed-off-by: Federico Vaga
Tested-by: Pat Riehecky
Acked-by: Alessandro Rubini
Signed-off-by: Greg Kroah-Hartman -
There is a mistake here where we accidentally use sizeof(TB_CFG_PKG_RESET)
instead of just TB_CFG_PKG_RESET. The size of an int is 4 so it's the
same as TB_CFG_PKG_NOTIFY_ACK.Fixes: d7f781bfdbf4 ("thunderbolt: Rework control channel to be more reliable")
Reported-by: Colin King
Signed-off-by: Dan Carpenter
Acked-by: Mika Westerberg
Cc: stable # 4.13
Signed-off-by: Greg Kroah-Hartman -
If secure authentication of a devices fails, either because the device
already has another key uploaded, or there is some other error sending
challenge to the device, and the user only wants to approve the device
just once (without a new key being uploaded to the device) the current
implementation does not allow this because the key cannot be cleared
once set even if we allow it to be changed.Make this scenario possible and allow clearing the key by writing
empty string to the key sysfs file.Signed-off-by: Yehezkel Bernat
Acked-by: Mika Westerberg
Signed-off-by: Greg Kroah-Hartman -
Non-root user may read the key back after root wrote it there.
This removes read access to everyone but root.Signed-off-by: Yehezkel Bernat
Acked-by: Mika Westerberg
Signed-off-by: Greg Kroah-Hartman -
The key size is tested by hex2bin() already (as '\0' isn't an hex digit)
Suggested-by: Andy Shevchenko
Signed-off-by: Yehezkel Bernat
Acked-by: Mika Westerberg
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
amba_id are not supposed to change at runtime. All functions
working with const amba_id. So mark the non-const structs as const.Signed-off-by: Arvind Yadav
Signed-off-by: Greg Kroah-Hartman -
The casting and other things here is odd, and causes sparse to
complain:drivers/hwtracing/coresight/coresight-stm.c:279:35: warning: incorrect type in argument 1 (different address spaces)
drivers/hwtracing/coresight/coresight-stm.c:279:35: expected void [noderef] *addr
drivers/hwtracing/coresight/coresight-stm.c:279:35: got struct stm_drvdata *drvdata
drivers/hwtracing/coresight/coresight-stm.c:327:17: warning: incorrect type in argument 2 (different address spaces)
drivers/hwtracing/coresight/coresight-stm.c:327:17: expected void volatile [noderef] *addr
drivers/hwtracing/coresight/coresight-stm.c:327:17: got void *addr
drivers/hwtracing/coresight/coresight-stm.c:330:17: warning: incorrect type in argument 2 (different address spaces)
drivers/hwtracing/coresight/coresight-stm.c:330:17: expected void volatile [noderef] *addr
drivers/hwtracing/coresight/coresight-stm.c:330:17: got void *addr
drivers/hwtracing/coresight/coresight-stm.c:333:17: warning: incorrect type in argument 2 (different address spaces)
drivers/hwtracing/coresight/coresight-stm.c:333:17: expected void volatile [noderef] *addr
drivers/hwtracing/coresight/coresight-stm.c:333:17: got void *addr>From what I can tell, we don't really need to treat ch_addr as
anything besides a pointer, and we can just do pointer math
instead of ORing in the bits of the offset and achieve the same
thing.Also, we were passing a drvdata pointer to the
coresight_timeout() function, but we really wanted to pass the
address of the register base. Luckily the base is the first
member of the structure, so everything works out, but this is
quite unsafe if we ever change the structure layout. Clean this
all up so sparse stops complaining on this code.Reported-by: Satyajit Desai
Signed-off-by: Stephen Boyd
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Add the peripheral ids for the Coresight SoC 600 TPIU, replicator
and funnel.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
The coresight SoC 600 supports ETR save-restore which allows us
to restore a trace session by retaining the RRP/RWP/STS.Full values
when the TMC leaves the Disabled state. However, the TMC doesn't
have a scatter-gather unit in built.Also, TMCs have different PIDs in different configurations (ETF,
ETB & ETR), unlike the previous generation.While the DEVID exposes some of the features/changes in the TMC,
it doesn't explicitly advertises the new save-restore feature
as described above.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
The Coresight SoC 600 TMC ETR supports save-restore feature,
where the values of the RRP/RWP and STS.Full are retained
when it leaves the Disabled state. Hence, we must program the
RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP
to the base address of the buffer and clear the STS.Full register.
This can be later exploited for proper save-restore of ETR
trace contexts (e.g, perf).Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Greg Kroah-Hartman -
If the ETR supports split cache encoding (i.e, separate bits for
read and write transfers) unlike the older version (where read
and write transfers use the same encoding in AXICTL[2-5]).
This feature is not advertised and has to be described by the
static mask associated with the device id.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
TMC in Coresight SoC-600 advertises the AXI address width
in the device configuration register.Bit 16 - AXIAW_VALID
0 - AXI Address Width not valid
1 - Valid AXI Address width in Bits[23-17]Bits [23-17] - AXIAW. If AXIAW_VALID = b01 then
0x20 - 32bit AXI address bus
0x28 - 40bit AXI address bus
0x2c - 44bit AXI address bus
0x30 - 48bit AXI address bus
0x34 - 52bit AXI address busUse the address bits from the device configuration register, if
available. Otherwise, default to 40bit.Cc: Mathieu Poirier
Cc: Robin Murphy
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
The SG unit in the TMC has been removed in Coresight SoC-600.
This is however advertised by DEVID:Bit 24 = 0b1. On the
previous generation, the bit is RES0, hence we can rely on the
DEVID to detect the support.Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
With new version of TMC ETR, there are differing set of
features supported by the TMC. Add the capability of a
given TMC ETR for making safer decisions at runtime.The device configuration register of the TMC (DEVID) lists
some of the capabilities. So, we can detect some of them at
probe. However, some of the features (or changes in behavior)
are not advertised and we have to depend on the PID to infer
the features. So we use a static description of the "unadvertised"
capabilities attached to the PID. Combining both, the static
and the dynamic capabilities, we maintain a bitmask of the
available features which can be later checked to take
appropriate actions.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. This would break
the existing driver which will treat anything other than ETR/ETB as an
ETF. Fix the driver to check the configuration type properly and also
add a warning if we encounter an unsupported configuration (ETS).Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Expose the idfilter* registers of the programmable replicator.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Expose DBALO,DBAHI and AXICTL registers
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Coresight TMC splits 64bit registers into a pair of 32bit registers
(e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Use the new helpers for exposing coresight component registers,
choosing the 64bit variants for appropriate registers.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Add support for reading a lower and upper 32bits of a register
as a single 64bit register. Also add simplified macros for
direct register accesses.Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
The Linux coresight drivers define the programmable ATB replicator as
Qualcomm replicator, while this is designed by ARM. This can cause
confusion to a user selecting the driver. Cleanup all references to
make it explicitly clear. This patch :1) Replace the compatible string for the replicator :
qcom,coresight-replicator1x => arm,coresight-dynamic-replicator
2) Changes the Kconfig symbol (since this is not part of any defconfigs)
CORESIGHT_QCOM_REPLICATOR => CORESIGHT_DYNAMIC_REPLICATOR
3) Improves the help message in the Kconfig.
4) Changes the name of the driver and the file :
coresight-replicator-qcom => coresight-dynamic-replicatorCc: Pratik Patel
Cc: Ivan T. Ivanov
Cc: Mathieu Poirier
Cc: devicetree@vger.kernel.org
Cc: Mark Rutland
Acked-by: Rob Herring
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Adds handling to program the return stack option into ETMv4 hardware if
specified in the perf command line.If option is not supported by the hardware then it will be ignored.
This allows capture to move between core/ETM combinations that have the
hardware support to those that do not.Signed-off-by: Mike Leach
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Adds handling to program the return stack option into PTM hardware if
specified in the perf command line.If option is not supported by the hardware then it will be ignored.
This allows capture to move between core/ETM combinations that have the
hardware support to those that do not.Signed-off-by: Mike Leach
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Return stack is a programmable option on some ETM and PTM hardware.
Adds the option flags to enable this from the perf event command line.Signed-off-by: Mike Leach
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
attribute_groups are not supposed to change at runtime. All functions
working with attribute_groups provided by work with const
attribute_group. So mark the non-const structs as const.File size before:
text data bss dec hex filename
2573 288 296 3157 c55 coresight-etm-perf.oFile size After adding 'const':
text data bss dec hex filename
2613 224 296 3133 c3d coresight-etm-perf.oSigned-off-by: Arvind Yadav
Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Register ETMSYNCFR holds the number of by that need to be generated before
periodic synchronisation packets are inserted in the trace stream. By
zeroing out the config structure, the current code effectively disable
periodic synchronization.This patch simply initialise the recommended value for this register as
specified in the technical reference manual.Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Function etb_disable_hw() is already taking care of unlocking and locking
the coresight access register and as such doesn't need to be placed
within the unlock/lock of function etb_update_buffer().Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
When a buffer overflow happens the synchronisation patckets usually
present at the beginning of the buffer are lost, a situation that
prevents the decoder from knowing the context of the traces being
decoded.This patch adds a barrier packet to be used by sink IPs when a buffer
overflow condition is detected. These barrier packets are then used
by the decoding library as markers to force re-synchronisation.Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Internal CoreSight components are rendering trace data in little-endian
format. As such there is no need to convert the data once more, hence
removing the extra step.Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman -
Many conditions may cause synchronisation to be lost when updating
the perf ring buffer but the end result is still the same: synchronisation
is lost. As such there is no need to increment the lost count for each
condition, just once will suffice.Signed-off-by: Mathieu Poirier
Signed-off-by: Greg Kroah-Hartman
