09 Jan, 2011
1 commit
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Added #define pr_fmt KBUILD_MODNAME ": " fmt
Converted printks to pr_
Coalesced any long formats
Removed prefixes from formatsSigned-off-by: Joe Perches
Signed-off-by: Guenter Roeck
18 Oct, 2010
1 commit
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The patch below updates broken web addresses in the kernel
Signed-off-by: Justin P. Mattock
Cc: Maciej W. Rozycki
Cc: Geert Uytterhoeven
Cc: Finn Thain
Cc: Randy Dunlap
Cc: Matt Turner
Cc: Dimitry Torokhov
Cc: Mike Frysinger
Acked-by: Ben Pfaff
Acked-by: Hans J. Koch
Reviewed-by: Finn Thain
Signed-off-by: Jiri Kosina
15 Sep, 2009
1 commit
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We had a report about a mainboard for AMD family 0Fh processors not
routing the 6th VID pin from the CPU to the hardware monitoring chip.While the vendor should have wired the pin (or, failing that, should
have hardwired it to level high rather than low), the fact is that
none of these processors are currently known to operate at the lower
voltage levels which require the 6th VID pin. So, as a practical
workaround, I propose to ignore the 6th VID pin for these CPUs.If this decision ever causes problems, we'll reconsider.
Signed-off-by: Jean Delvare
Cc: Frank Myhr
Tested-by: Hleb Valoshka
Cc: Rudolf Marek
Cc: Andreas Herrmann
27 Oct, 2008
1 commit
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The AMD family 10h CPUs use the same VID decoding table as the family
0Fh CPUs.Signed-off-by: Jean Delvare
Cc: Rudolf Marek
16 Aug, 2008
1 commit
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Not all AMD K8 have 6 VID pins, contrary to what was assumed in
commit 116d0486bdefc11f71e567cadf0c47f788b4dd06. This commit broke
support of older CPU models which have only 5 VID pins:
http://bugzilla.kernel.org/show_bug.cgi?id=11329We need two entries in the hwmon-vid table, one for 5-bit VID models
(K8 revision = F).
This fixes bug #11329.Signed-off-by: Jean Delvare
Acked-by: Frank Myhr
Tested-by: Jean-Luc Coulon
Signed-off-by: Linus Torvalds
07 Aug, 2008
2 commits
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AMD NPT 0Fh cpus use 6 bit VID codes. Successive codes with msb 0
describe 25mV decrements, while those with msb 1 describe 12.5mV
decrements. Existing hwmon-vid.c is correct only for codes with msb 0;
add support for the codes with msb 1.Ref:
p 309, Table 71
AMD Publication 32559, BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdfSigned-off-by: Frank Myhr
Signed-off-by: Jean Delvare -
Signed-off-by: Frank Myhr
Signed-off-by: Jean Delvare
20 Oct, 2007
1 commit
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cpu_data is currently an array defined using NR_CPUS. This means that
we overallocate since we will rarely really use maximum configured cpus.
When NR_CPU count is raised to 4096 the size of cpu_data becomes
3,145,728 bytes.These changes were adopted from the sparc64 (and ia64) code. An
additional field was added to cpuinfo_x86 to be a non-ambiguous cpu
index. This corresponds to the index into a cpumask_t as well as the
per_cpu index. It's used in various places like show_cpuinfo().cpu_data is defined to be the boot_cpu_data structure for the NON-SMP
case.Signed-off-by: Mike Travis
Acked-by: Christoph Lameter
Cc: Andi Kleen
Cc: James Bottomley
Cc: Dmitry Torokhov
Cc: "Antonino A. Daplas"
Cc: Mark M. Hoffman
Signed-off-by: Andrew Morton
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
28 May, 2007
1 commit
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If we cannot guess which VRM version the CPU uses, we set it to 0 and
log it. So we shouldn't spam the log each time vid_from_reg() is
later called with vrm 0.Signed-off-by: Jean Delvare
Acked-by: Rudolf Marek
08 May, 2007
1 commit
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Update the VID type for certain VIA processors and remove
the Itanium entries.Signed-off-by: Rudolf Marek
Signed-off-by: Jean Delvare
19 Jan, 2007
1 commit
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I wonder how we came up with such a broken test in the first place.
Signed-off-by: Jean Delvare
13 Dec, 2006
1 commit
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The Silicon Hill club is not what it used to be.
Signed-off-by: Rudolf Marek
Signed-off-by: Jean Delvare
01 Jul, 2006
1 commit
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Signed-off-by: Jörn Engel
Signed-off-by: Adrian Bunk
23 Jun, 2006
2 commits
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This patch adds support for two new VID codes, supporting Intel mobile Core
processors and new Conroe based platforms.Signed-off-by: Rudolf Marek
Signed-off-by: Jean Delvare
Signed-off-by: Greg Kroah-Hartman -
Following patch trims the VID value to correct number of bits
for each VRM.Signed-off-by: Rudolf Marek
Signed-off-by: Jean Delvare
Signed-off-by: Greg Kroah-Hartman
24 Mar, 2006
1 commit
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Add support for the Intel Pentium M series to the hwmon-vid driver.
Signed-off-by: Jean Delvare
Cc: Rudolf Marek
Signed-off-by: Greg Kroah-Hartman
06 Jan, 2006
1 commit
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This patch adds the VIA CENTAUR CPUs to detection table.
Table was updated to treat future Intel x86 CPUs as VRD10.
Stepping field was added, because some VIA CPUs have
different VRM specs across stepping. I changed the vrm type
to u8 because all drivers use u8 anyway.Signed-off-by: Rudolf Marek
Signed-off-by: Jean Delvare
Signed-off-by: Greg Kroah-Hartman
06 Sep, 2005
4 commits
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This patch updates the VID entries, so any future
Intel CPU will be detected as unknown rather than 9.0Signed-off-by: Rudolf Marek
Signed-off-by: Greg Kroah-Hartman -
I see very little reason why vid_from_reg is inlined. It is not
exactly short, its parameters are seldom known in advance, and it is
never called in speed critical areas. Uninlining it should cause
little performance loss if any, and saves a signficant space as well
as compilation time.As suggested by Alexey Dobriyan, I am leaving vid_to_reg inline for now,
as it is short and has a single user so far.Signed-off-by: Jean Delvare
Signed-off-by: Greg Kroah-Hartman -
Cleanup hwmon-vid a bit, fixing typos, rewording some comments and
reindenting properly at places.Signed-off-by: Jean Delvare
Signed-off-by: Greg Kroah-Hartman -
The only part left in i2c-sensor is the VRM/VRD/VID handling code.
This is in no way related to i2c, so it doesn't belong there. Move
the code to hwmon, where it belongs.Note that not all hardware monitoring drivers do VRM/VRD/VID
operations, so less drivers depend on hwmon-vid than there were
depending on i2c-sensor.Signed-off-by: Jean Delvare
Signed-off-by: Greg Kroah-Hartman