12 Nov, 2020
1 commit
-
Add USB PHY tuning of imx8mq/p for USB certification, mainly for eye
diagram test.Reviewed-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit 2ad925d1548144d2ce6cb7301e213ca1a9c326a4)
08 Oct, 2020
1 commit
-
* tag 'v5.4.70': (3051 commits)
Linux 5.4.70
netfilter: ctnetlink: add a range check for l3/l4 protonum
ep_create_wakeup_source(): dentry name can change under you...
...Conflicts:
arch/arm/mach-imx/pm-imx6.c
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
drivers/crypto/caam/caamalg.c
drivers/gpu/drm/imx/dw_hdmi-imx.c
drivers/gpu/drm/imx/imx-ldb.c
drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c
drivers/mmc/host/sdhci-esdhc-imx.c
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
drivers/net/ethernet/freescale/enetc/enetc.c
drivers/net/ethernet/freescale/enetc/enetc_pf.c
drivers/thermal/imx_thermal.c
drivers/usb/cdns3/ep0.c
drivers/xen/swiotlb-xen.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.cSigned-off-by: Jason Liu
07 Oct, 2020
1 commit
-
[ Upstream commit ac67b07e268d46eba675a60c37051bb3e59fd201 ]
Currently, the aspeed-sgpio driver exposes up to 80 GPIO lines,
corresponding to the 80 status bits available in hardware. Each of these
lines can be configured as either an input or an output.However, each of these GPIOs is actually an input *and* an output; we
actually have 80 inputs plus 80 outputs.This change expands the maximum number of GPIOs to 160; the lower half
of this range are the input-only GPIOs, the upper half are the outputs.
We fix the GPIO directions to correspond to this mapping.This also fixes a bug when setting GPIOs - we were reading from the
input register, making it impossible to set more than one output GPIO.Signed-off-by: Jeremy Kerr
Fixes: 7db47faae79b ("gpio: aspeed: Add SGPIO driver")
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Acked-by: Rob Herring
Signed-off-by: Bartosz Golaszewski
Signed-off-by: Sasha Levin
01 Oct, 2020
1 commit
-
[ Upstream commit 8c149b7d75e53be47648742f40fc90d9fc6fa63a ]
The required supplies in bindings were actually not matching
implementation making the bindings incorrect and misleading. The Linux
kernel driver requires all supplies to be present. Also for wlf,wm8994
uses just DBVDD-supply instead of DBVDDn-supply (n: ).Reported-by: Jonathan Bakker
Signed-off-by: Krzysztof Kozlowski
Link: https://lore.kernel.org/r/20200501133534.6706-1-krzk@kernel.org
Signed-off-by: Mark Brown
Signed-off-by: Sasha Levin
22 Sep, 2020
1 commit
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Add a new compatible string "raydium,rm67199" for the new version of
this panel, similar with rm67191 which is also supported by the same
driver.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu
10 Sep, 2020
1 commit
-
commit 65557383191de46611dd3d6b639cbcfbade43c4a upstream.
Add description for resets/reset-names.
Cc: # v5.4+
Fixes: 966580ad236e ("mmc: mediatek: add support for MT7622 SoC")
Signed-off-by: Wenbin Mei
Tested-by: Frank Wunderlich
Link: https://lore.kernel.org/r/20200814014346.6496-2-wenbin.mei@mediatek.com
Signed-off-by: Ulf Hansson
Signed-off-by: Greg Kroah-Hartman
05 Sep, 2020
1 commit
-
commit f7f86e8ac0ad7cd6792a80137f5a550924966916 upstream.
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
Tegra210 and later uses separate SDMMC_LEGACY_TM clock for data
timeout.So, this patch adds "tmclk" to Tegra sdhci clock property in the
device tree binding.Fixes: b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
Cc: stable # 5.4
Reviewed-by: Jon Hunter
Signed-off-by: Sowjanya Komatineni
Link: https://lore.kernel.org/r/1598548861-32373-4-git-send-email-skomatineni@nvidia.com
Signed-off-by: Ulf Hansson
Signed-off-by: Greg Kroah-Hartman
21 Aug, 2020
2 commits
-
Add dt-bindings documentation for WKS 101wx001 paralel LCD panel.
Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
commit add48ba425192c6e04ce70549129cacd01e2a09e upstream.
The correct compatible string is "gpio-mux" (see
bindings/mux/gpio-mux.txt).Cc: stable@vger.kernel.org # v4.13+
Reviewed-by: Peter Rosin
Signed-off-by: Christian Eggers
Link: https://lore.kernel.org/r/20200727101605.24384-1-ceggers@arri.de
Signed-off-by: Rob Herring
Signed-off-by: Greg Kroah-Hartman
20 Aug, 2020
1 commit
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Add vbus-power-supply property for BC battery charger, which is the
phandle of power supply of vbus.Reviewed-by: Peter Chen
Signed-off-by: Li Jun
22 Jul, 2020
2 commits
-
[ Upstream commit 3d157c28d2289edf0439e8308e8de3a06acaaf0e ]
This patch updates the documentation with the information related
to the quirks that needs to be added for disabling all SuperSpeed XHCI
instances in park mode.Cc: Dongjin Kim
Cc: Jianxin Pan
Cc: Thinh Nguyen
Cc: Jun Li
Reported-by: Tim
Signed-off-by: Neil Armstrong
Acked-by: Rob Herring
Signed-off-by: Felipe Balbi
Signed-off-by: Sasha Levin -
[ Upstream commit 35b9c0fdb9f666628ecda02b1fc44306933a2d97 ]
Fix unit address to match the first address specified in the reg
property of the node in example.Signed-off-by: Kangmin Park
Link: https://lore.kernel.org/r/20200625135158.5861-1-l4stpr0gr4m@gmail.com
Signed-off-by: Rob Herring
Signed-off-by: Sasha Levin
10 Jul, 2020
1 commit
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The DTS is for i.MX8MP DSP offload audio playback. DSP only use OCRAM
and OCRAM_A when audio playback, so DRAM can enter retention mode to
save Power. As the size limitation of OCRAM and OCRAM_A and the size
audio decoder library, the LPA playback only can support MP3 and AAC.
OCRAM address is 0x900000-0x990000. ATF will use 0x960000-0x980000.
DSP LPA will use ocram(0x900000-0x960000) and ocram_e(0x980000-
0x990000)Signed-off-by: Bing Song
24 Jun, 2020
1 commit
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Update the clock modes of iMX8MP PCIe PHY in binding DOC.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
22 Jun, 2020
1 commit
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[ Upstream commit b0ff9b590733079f7f9453e5976a9dd2630949e3 ]
Add property "pinctrl-names" to swap pin mode between gpio and dpi mode.
Set the dpi pins to gpio mode and output-low to avoid leakage current
when dpi disabled.Acked-by: Rob Herring
Signed-off-by: Jitao Shi
Signed-off-by: Chun-Kuang Hu
Signed-off-by: Sasha Levin
19 Jun, 2020
1 commit
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* tag 'v5.4.47': (2193 commits)
Linux 5.4.47
KVM: arm64: Save the host's PtrAuth keys in non-preemptible context
KVM: arm64: Synchronize sysreg state on injecting an AArch32 exception
...Conflicts:
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/common.h
arch/arm/mach-imx/suspend-imx6.S
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
arch/powerpc/include/asm/cacheflush.h
drivers/cpufreq/imx6q-cpufreq.c
drivers/dma/imx-sdma.c
drivers/edac/synopsys_edac.c
drivers/firmware/imx/imx-scu.c
drivers/net/ethernet/freescale/fec.h
drivers/net/ethernet/freescale/fec_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
drivers/net/phy/phy_device.c
drivers/perf/fsl_imx8_ddr_perf.c
drivers/usb/cdns3/gadget.c
drivers/usb/dwc3/gadget.c
include/uapi/linux/dma-buf.hSigned-off-by: Jason Liu
11 Jun, 2020
1 commit
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Add the iMX PCIe endpoint mode supports.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
10 Jun, 2020
1 commit
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Add dt property for user to enable clkout for MAC.
Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
27 May, 2020
1 commit
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Add "fsl,spi-only-use-cs1-sel" to fit i.MX8DXL-EVK.
Spi common code does not support use of CS signals discontinuously.
It only uses CS1 without using CS0. So, add this property to re-config
chipselect value.Signed-off-by: Clark Wang
Reviewed-by: Fugang Duan
22 May, 2020
1 commit
-
This is an adapter card made for the 4.3", 800x480, LCD panel Seiko
43WVFIG. The LCD panel is a 24bit DPI bus, while the adapter card has
two ports: 18-bit and 24-bit data input. For the 18-bit data input, the
adapter card is demuxing some of the data lines, in order to feed all of
the 24 lines needed by the LCD.
This driver handles both this use-cases.Signed-off-by: Robert Chiras
23 Apr, 2020
1 commit
-
[ Upstream commit f9f711efd441ad0d22874be49986d92121862335 ]
If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled
then this can cause the kernel to incorrectly probe the generic
designware PCIe platform driver instead of the Tegra194 designware PCIe
driver. This causes a boot failure on Tegra194 because the necessary
configuration to access the hardware is not performed.The order in which the compatible strings are populated in Device-Tree
is not relevant in this case, because the kernel will attempt to probe
the device as soon as a driver is loaded and if the generic designware
PCIe driver is loaded first, then this driver will be probed first.
Therefore, to fix this problem, remove the "snps,dw-pcie" string from
the compatible string as we never want this driver to be probe on
Tegra194.Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT")
Signed-off-by: Jon Hunter
Signed-off-by: Thierry Reding
Signed-off-by: Sasha Levin
22 Apr, 2020
1 commit
-
The V2X MU requires that the the sender changes the byte indication
the type of the message in its header. The value required changes
for each MU.This patch adds the documentation of this functionality adding
explanations for fsl,cmd_tag and fsl,rsp_tag.Signed-off-by: Stéphane Dion
10 Apr, 2020
1 commit
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DPU found in i.MX8qxp SoC may drive a parallel display through
pixel link to LCDIF mux. This patch adds the device tree binding
documentation for LCDIF mux display.Reviewed-by: Robert Chiras
Tested-by: Robert Chiras
Signed-off-by: Liu Ying
09 Apr, 2020
2 commits
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Support i.MX8/8M/7ULP:
- Introduce early-booted property for M4 booted before Linux
- Introduce mboxes for rpmsg/virtio to communicate with M4
- Introduce mub-partition for hardware partition supported by i.MX8
- Introduce rsrc-table which hold the resource table
- Introduce rsrc-daReviewed-by: Richard Zhu
Signed-off-by: Peng Fan -
Convert the i.MX remoteproc binding to DT schema format
using json-schemaReviewed-by: Richard Zhu
Signed-off-by: Peng Fan
01 Apr, 2020
1 commit
-
[ Upstream commit 26d5bb9e4c4b541c475751e015072eb2cbf70d15 ]
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.Signed-off-by: Madalin Bucur
Signed-off-by: David S. Miller
Signed-off-by: Sasha Levin
31 Mar, 2020
2 commits
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For dwc3-imx8mp, the clock for its power domain hsiomix has
to be handled by user, so add the hsio root clock to dwc3 imx8mp
binding doc.Reviewed-by: Peter Chen
Signed-off-by: Li Jun -
Document newly supported device tree properties max-cs to specify the
maximum cs the board supports.Signed-off-by: Han Xu
26 Mar, 2020
1 commit
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Some power domain need to be runtime always on to keep
the peripherals's weekup ability, for such power domain,
add the 'GENPD_FLAG_RPM_ALWAYS_ON' flag.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
18 Mar, 2020
2 commits
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The phy registers are accessible after APB clock is enabled.
So, add the relevant clock properties in device tree doc.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
Add the active wakeup flag if a power domain has such requirement.
Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
14 Mar, 2020
1 commit
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Add the documentation for fsl,imx-secvio-sc binding.
Signed-off-by: Franck LENORMAND
12 Mar, 2020
2 commits
-
Signed-off-by: Franck LENORMAND
-
i.MX8/8X SECO MU is dedicated for communication between kernel
and SECO. To use SECO MU more effectivly, add "fsl,imx8-seco-mu"
compatible to support fast IPC.Signed-off-by: Peng Fan
Signed-off-by: Franck LENORMAND
08 Mar, 2020
1 commit
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Merge Linux stable release v5.4.24 into imx_5.4.y
* tag 'v5.4.24': (3306 commits)
Linux 5.4.24
blktrace: Protect q->blk_trace with RCU
kvm: nVMX: VMWRITE checks unsupported field before read-only field
...Signed-off-by: Jason Liu
Conflicts:
arch/arm/boot/dts/imx6sll-evk.dts
arch/arm/boot/dts/imx7ulp.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
drivers/clk/imx/clk-composite-8m.c
drivers/gpio/gpio-mxc.c
drivers/irqchip/Kconfig
drivers/mmc/host/sdhci-of-esdhc.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
drivers/net/can/flexcan.c
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
drivers/net/ethernet/mscc/ocelot.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
drivers/net/phy/realtek.c
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
drivers/perf/fsl_imx8_ddr_perf.c
drivers/tee/optee/shm_pool.c
drivers/usb/cdns3/gadget.c
kernel/sched/cpufreq.c
net/core/xdp.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.c
sound/soc/sof/core.c
sound/soc/sof/imx/Kconfig
sound/soc/sof/loader.c
04 Mar, 2020
2 commits
-
Add driver support for i.MX8DXL DB Perf, which supports AXI ID PORT
CHANNEL filter.Reviewed-by: Fugang Duan
Signed-off-by: Joakim Zhang -
Add driver support for i.MX8DXL DDR Perf, which supports AXI ID PORT
CHANNEL filter.Reviewed-by: Fugang Duan
Signed-off-by: Joakim Zhang
26 Feb, 2020
2 commits
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Add documentation for a new clock 'phy_parent'. This clock is optional
and is used to re-parent the PHY related clocks (phy_ref, tx_esc and
rx_esc) to a valid parent. This clock is needed, in order to make the
re-parenting in driver, since the default re-parenting in dts node
(using assigned-clock-parents) may break the LVDS block, which has it's
PHY shared with MIPI-DSI.Signed-off-by: Robert Chiras
Signed-off-by: Dong Aisheng
(cherry picked from commit 7ed3b8738e3103396a5f3a9268c66f11f78cab03) -
QORIQ LS1028A soc used fsl,vf610-edma, but it has a little bit different
from others, so add new compatible to distinguish them.Signed-off-by: Peng Ma
Link: https://lore.kernel.org/r/20191212033714.4090-3-peng.ma@nxp.com
Signed-off-by: Vinod Koul
(cherry picked from commit f8dd1f395d1fbba049900ed48c09d76df49be712)
21 Feb, 2020
1 commit
-
Signed-off-by: Franck LENORMAND
(cherry picked from commit f23aa19e875f7ca786c50116ad1b4b7c04625628)