24 Sep, 2019
6 commits
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Fix typos in drivers/ntb/hw/idt/Kconfig.
Use consistent spelling and capitalization.Fixes: bf2a952d31d2 ("NTB: Add IDT 89HPESxNTx PCIe-switches support")
Signed-off-by: Randy Dunlap
Cc: Dave Jiang
Cc: Allen Hubbe
Cc: Serge Semin
Signed-off-by: Jon Mason -
The AMD new hardware uses BAR23 and BAR45 as memory windows
as compared to previos where BAR1, BAR23 and BAR45 is used
for memory windows.This patch add support for both AMD hardwares.
Signed-off-by: Sanjay R Mehta
Signed-off-by: Jon Mason -
Signed-off-by: Sanjay R Mehta
Signed-off-by: Jon Mason -
Variable rc is initialized to a value that is never read and it
is re-assigned later. The initialization is redundant and can be
removed.Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
Signed-off-by: Jon Mason -
On switchtec_ntb_mw_set_trans() call, when (only) address == 0, it acts as
ntb_mw_clear_trans(). Fix this, since address == 0 and size != 0 is valid
combination for setting translation.Signed-off-by: Alexander Fomichev
Reviewed-by: Logan Gunthorpe
Signed-off-by: Jon Mason -
second parameter of ntb_peer_mw_get_addr is pointing to wrong memory
window index by passing "peer gidx" instead of "local gidx".For ex, "local gidx" value is '0' and "peer gidx" value is '1', then
on peer side ntb_mw_set_trans() api is used as below with gidx pointing to
local side gidx which is '0', so memroy window '0' is chosen and XLAT '0'
will be programmed by peer side.ntb_mw_set_trans(perf->ntb, peer->pidx, peer->gidx, peer->inbuf_xlat,
peer->inbuf_size);Now, on local side ntb_peer_mw_get_addr() is been used as below with gidx
pointing to "peer gidx" which is '1', so pointing to memory window '1'
instead of memory window '0'.ntb_peer_mw_get_addr(perf->ntb, peer->gidx, &phys_addr,
&peer->outbuf_size);So this patch pass "local gidx" as parameter to ntb_peer_mw_get_addr().
Signed-off-by: Sanjay R Mehta
Signed-off-by: Jon Mason
06 Aug, 2019
1 commit
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msi.c is not a module on its own right and should not have the
MODULE_[LICENSE|VERSION|AUTHOR|DESCRIPTION] definitions.This caused a regression noticed by lkp with the following back
trace:WARNING: CPU: 0 PID: 1 at kernel/params.c:861 param_sysfs_init+0xb1/0x20a
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-00018-g26b3a37b928457 #2
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.10.2-1 04/01/2014
RIP: 0010:param_sysfs_init+0xb1/0x20a
Code: 24 38 e8 ec 17 2e fd 49 8b 7c 24 38 e8 76 fe ff ff 48 85 c0 48 89 c5 74 25 31 d2 4c 89 e6 48 89 c7 e8 6d 6f 3c fd 85 c0 74 02 0b 48 89 ef 31 f6 e8 5d 70 a7 fe 48 89 ef e8 95 52 a7 fe 48 83
RSP: 0000:ffff88806b0ffe30 EFLAGS: 00010282
RAX: 00000000ffffffef RBX: ffffffff83774220 RCX: ffff88806a85e880
RDX: 00000000ffffffef RSI: ffff88806b000400 RDI: ffff88806a8608c0
RBP: ffff88806b392000 R08: ffffed100d61ff59 R09: ffffed100d61ff59
R10: 0000000000000001 R11: ffffed100d61ff58 R12: ffffffff83974bc0
R13: 0000000000000004 R14: 0000000000000028 R15: 00000000000003b9
FS: 0000000000000000(0000) GS:ffff88806b800000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000000 CR3: 000000000380e000 CR4: 00000000000406b0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Call Trace:
? file_caps_disable+0x10/0x10
? locate_module_kobject+0xf2/0xf2
do_one_initcall+0x47/0x1f0
kernel_init_freeable+0x1b1/0x243
? rest_init+0xd0/0xd0
kernel_init+0xa/0x130
? calculate_sigpending+0x63/0x80
? rest_init+0xd0/0xd0
ret_from_fork+0x1f/0x30
---[ end trace 78201497ae74cc91 ]---Reported-by: kernel test robot
Fixes: 26b3a37b9284 ("NTB: Introduce MSI library")
Signed-off-by: Logan Gunthorpe
Signed-off-by: Jon Mason
22 Jul, 2019
1 commit
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Pull NTB updates from Jon Mason:
"New feature to add support for NTB virtual MSI interrupts, the ability
to test and use this feature in the NTB transport layer.Also, bug fixes for the AMD and Switchtec drivers, as well as some
general patches"* tag 'ntb-5.3' of git://github.com/jonmason/ntb: (22 commits)
NTB: Describe the ntb_msi_test client in the documentation.
NTB: Add MSI interrupt support to ntb_transport
NTB: Add ntb_msi_test support to ntb_test
NTB: Introduce NTB MSI Test Client
NTB: Introduce MSI library
NTB: Rename ntb.c to support multiple source files in the module
NTB: Introduce functions to calculate multi-port resource index
NTB: Introduce helper functions to calculate logical port number
PCI/switchtec: Add module parameter to request more interrupts
PCI/MSI: Support allocating virtual MSI interrupts
ntb_hw_switchtec: Fix setup MW with failure bug
ntb_hw_switchtec: Skip unnecessary re-setup of shared memory window for crosslink case
ntb_hw_switchtec: Remove redundant steps of switchtec_ntb_reinit_peer() function
NTB: correct ntb_dev_ops and ntb_dev comment typos
NTB: amd: Silence shift wrapping warning in amd_ntb_db_vector_mask()
ntb_hw_switchtec: potential shift wrapping bug in switchtec_ntb_init_sndev()
NTB: ntb_transport: Ensure qp->tx_mw_dma_addr is initaliazed
NTB: ntb_hw_amd: set peer limit register
NTB: ntb_perf: Clear stale values in doorbell and command SPAD register
NTB: ntb_perf: Disable NTB link after clearing peer XLAT registers
...
13 Jun, 2019
15 commits
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Introduce the module parameter 'use_msi' which, when set, uses
MSI interrupts instead of doorbells for each queue pair (QP). The
parameter is only available if NTB MSI support is configured into
the kernel. We also require there to be more than one memory window
(MW) so that an extra one is available to forward the APIC region.To use MSIs, we request one interrupt per QP and forward the MSI address
and data to the peer using scratch pad registers (SPADS) above the MW
SPADS. (If there are not enough SPADS the MSI interrupt will not be used.)Once registered, we simply use ntb_msi_peer_trigger and the receiving
ISR simply queues up the rxc_db_work for the queue.This addition can significantly improve performance of ntb_transport.
In a simple, untuned, apples-to-apples comparision using ntb_netdev
and iperf with switchtec hardware, I see 3.88Gb/s without MSI
interrupts and 14.1Gb/s wit MSI, which is a more than 3x improvement.Signed-off-by: Logan Gunthorpe
Cc: Dave Jiang
Cc: Allen Hubbe
Signed-off-by: Jon Mason -
Introduce a tool to test NTB MSI interrupts similar to the other
NTB test tools. This tool creates a debugfs directory for each
NTB device with the following files:port
irqX_occurrences
peerX/port
peerX/count
peerX/triggerThe 'port' file tells the user the local port number and the
'occurrences' files tell the number of local interrupts that
have been received for each interrupt.For each peer, the 'port' file and the 'count' file tell you the
peer's port number and number of interrupts respectively. Writing
the interrupt number to the 'trigger' file triggers the interrupt
handler for the peer which should increment their corresponding
'occurrences' file. The 'ready' file indicates if a peer is ready,
writing to this file blocks until it is ready.The module parameter num_irqs can be used to set the number of
local interrupts. By default this is 4. This is only limited by
the number of unused MSI interrupts registered by the hardware
(this will require support of the hardware driver) and there must
be at least 2*num_irqs + 1 spads registers available.Signed-off-by: Logan Gunthorpe
Cc: Dave Jiang
Cc: Allen Hubbe
Signed-off-by: Jon Mason -
The NTB MSI library allows passing MSI interrupts across a memory
window. This offers similar functionality to doorbells or messages
except will often have much better latency and the client can
potentially use significantly more remote interrupts than typical hardware
provides for doorbells. (Which can be important in high-multiport
setups.)The library utilizes one memory window per peer and uses the highest
index memory windows. Before any ntb_msi function may be used, the user
must call ntb_msi_init(). It may then setup and tear down the memory
windows when the link state changes using ntb_msi_setup_mws() and
ntb_msi_clear_mws().The peer which receives the interrupt must call ntb_msim_request_irq()
to assign the interrupt handler (this function is functionally
similar to devm_request_irq()) and the returned descriptor must be
transferred to the peer which can use it to trigger the interrupt.
The triggering peer, once having received the descriptor, can
trigger the interrupt by calling ntb_msi_peer_trigger().Signed-off-by: Logan Gunthorpe
Cc: Dave Jiang
Cc: Allen Hubbe
Signed-off-by: Jon Mason -
The kbuild system does not support having multiple source files in
a module if one of those source files has the same name as the module.Therefore, we must rename ntb.c to core.c, while the module remains
ntb.ko.This is similar to the way the nvme modules are structured.
Signed-off-by: Logan Gunthorpe
Cc: Dave Jiang
Cc: Allen Hubbe
Signed-off-by: Jon Mason -
Switchtec does not support setting multiple MWs simultaneously. The
driver takes a hardware lock to ensure that two peers are not doing this
simultaneously and it fails if someone else takes the lock. In most
cases, this is fine as clients only setup the MWs once on one side of
the link.However, there's a race condition when a re-initialization is caused by
a link event. The driver will re-setup the shared memory window
asynchronously and this races with the client setting up it's memory
windows on the link up event.To fix this we ensure do the entire initialization in a work queue and
signal the client once it's done.Signed-off-by: Joey Zhang
Signed-off-by: Wesley Sheng
Signed-off-by: Jon Mason -
In case of NTB crosslink topology, the setting of shared memory window in
the virtual partition doesn't reset on peer's reboot. So skip the
unnecessary re-setup of shared memory window for that case.Signed-off-by: Wesley Sheng
Signed-off-by: Jon Mason -
When a re-initialization is caused by a link event, the driver will
re-setup the shared memory window. But at that time, the shared memory
is still valid, and it's unnecessary to free, reallocate and then
initialize it again. We only need to reconfigure the hardware
registers. Remove the redundant steps from
switchtec_ntb_reinit_peer() function.Signed-off-by: Joey Zhang
Signed-off-by: Wesley Sheng
Reviewed-by: Logan Gunthorpe
Signed-off-by: Jon Mason -
This code triggers a Smatch warning:
drivers/ntb/hw/amd/ntb_hw_amd.c:336 amd_ntb_db_vector_mask()
warn: should '(1 << db_vector)' be a 64 bit type?I don't think "db_vector" can be higher than 16 so this doesn't affect
runtime, but it's nice to silence the static checker warning and we
might increase "ndev->db_count" in the future.Signed-off-by: Dan Carpenter
Acked-by: Shyam Sundar S K
Signed-off-by: Jon Mason -
This code triggers a Smatch warning:
drivers/ntb/hw/mscc/ntb_hw_switchtec.c:884 switchtec_ntb_init_sndev()
warn: should '(1 << sndev->peer_partition)' be a 64 bit type?The "part_map" and "tpart_vec" variables are u64 type so this seems like
a valid warning.Fixes: 3df54c870f52 ("ntb_hw_switchtec: Allow using Switchtec NTB in multi-partition setups")
Signed-off-by: Dan Carpenter
Reviewed-by: Logan Gunthorpe
Signed-off-by: Jon Mason -
Dan Carpenter's static checker reported:
drivers/ntb/ntb_transport.c:1926 ntb_transport_create_queue()
error: we previously assumed 'qp->tx_dma_chan' could be null (see line 1872)This is because the tx_mw_dma_addr is uninitialized in this function and
may be incorrectly released using a NULL DMA channel.In practice this bug will not likely be seen. I'd guess you could hit
this if you loaded ntb_netdev with use_dma=True, then unloaded it and
loaded it again after setting the module parameter to use_dma=False.To fix this, we simply ensure that tx_mw_dma_addr is always
initialized to zero. This is the safest in case any other part of the
code operates on it if it is non-zero.Fixes: c59666bb32b9 ("NTB: ntb_transport: Ensure the destination buffer is mapped for TX DMA")
Signed-off-by: Logan Gunthorpe
Cc: Dan Carpenter
Signed-off-by: Jon Mason -
As per amd ntb spec it says that peer limit register
must be programmedSigned-off-by: Sanjay R Mehta
Acked-by: Allen Hubbe
Acked-by: Logan Gunthorpe
Acked-by: Serge Semin
Signed-off-by: Jon Mason -
when ntb_perf is unloaded, the command scratchpad register still
retains the last initialized value of PERF_CMD_INVAL. When ntb_perf
is re-loaded and reads peer command scratchpad register and it mis
interprets the peer state as initialized.To avoid this, clearing the local side command scratchpad register
in perf_disable_serviceSigned-off-by: Sanjay R Mehta
Acked-by: Allen Hubbe
Acked-by: Logan Gunthorpe
Acked-by: Serge Semin
Signed-off-by: Jon Mason -
If ntb link disabled before clearing peer's XLAT register, the clearing
won't have any effect since the link is already down. So modified the
sequence so that the link is down only towards the end of the function
after clearing the XLAT registerSigned-off-by: Sanjay R Mehta
Acked-by: Allen Hubbe
Acked-by: Logan Gunthorpe
Acked-by: Serge Semin
Signed-off-by: Jon Mason -
while waiting for the peer ntb_perf to initialize scratchpad
registers, local side ntb_perf might have already exhausted the
maximum number of retries which is currently set to 500. To avoid
this and to give little more time to the peer ntb_perf for scratchpad
initialization, increased the number of retries to 1000Signed-off-by: Sanjay R Mehta
Acked-by: Allen Hubbe
Acked-by: Logan Gunthorpe
Acked-by: Serge Semin
Signed-off-by: Jon Mason -
Fix sparse warning:
drivers/ntb/hw/intel/ntb_hw_gen3.c:535:5: warning:
symbol 'intel_ntb3_peer_db_addr' was not declared. Should it be static?Signed-off-by: YueHaibing
Acked-by: Dave Jiang
Signed-off-by: Jon Mason
05 Jun, 2019
1 commit
-
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more detailsextracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 263 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Allison Randal
Reviewed-by: Alexios Zavras
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de
Signed-off-by: Greg Kroah-Hartman
21 May, 2019
1 commit
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:GPL-2.0-only
Signed-off-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
08 Apr, 2019
1 commit
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mmiowb() is now implied by spin_unlock() on architectures that require
it, so there is no reason to call it from driver code. This patch was
generated using coccinelle:@mmiowb@
@@
- mmiowb();and invoked as:
$ for d in drivers include/linux/qed sound; do \
spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; doneNOTE: mmiowb() has only ever guaranteed ordering in conjunction with
spin_unlock(). However, pairing each mmiowb() removal in this patch with
the corresponding call to spin_unlock() is not at all trivial, so there
is a small chance that this change may regress any drivers incorrectly
relying on mmiowb() to order MMIO writes between CPUs using lock-free
synchronisation. If you've ended up bisecting to this commit, you can
reintroduce the mmiowb() calls using wmb() instead, which should restore
the old behaviour on all architectures other than some esoteric ia64
systems.Acked-by: Linus Torvalds
Signed-off-by: Will Deacon
16 Mar, 2019
1 commit
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Pull NTB updates from Jon Mason:
- fixes for switchtec debugability and mapping table entries
- NTB transport improvements
- a reworking of the peer_db_addr for better abstraction
* tag 'ntb-5.1' of git://github.com/jonmason/ntb:
NTB: add new parameter to peer_db_addr() db_bit and db_data
NTB: ntb_transport: Ensure the destination buffer is mapped for TX DMA
NTB: ntb_transport: Free MWs in ntb_transport_link_cleanup()
ntb_hw_switchtec: Added support of >=4G memory windows
ntb_hw_switchtec: NT req id mapping table register entry number should be 512
ntb_hw_switchtec: debug print 64bit aligned crosslink BAR Numbers
14 Feb, 2019
1 commit
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NTB door bell usage depends on NTB hardware.
ex: intel NTB gen1 has one peer door bell register which can be controlled
by the bitmap writen to it, while Intel NTB gen3 has a registers
per door bell and the data trigering the each door bell is always 1.therefore exposing only peer door bell address forcing the user
to be aware of such low level detailsSigned-off-by: Leonid Ravich
Acked-by: Logan Gunthorpe
Acked-by: Dave Jiang
Acked-by: Allen Hubbe
Signed-off-by: Jon Mason
11 Feb, 2019
4 commits
-
Presently, when ntb_transport is used with DMA and the IOMMU turned on,
it fails with errors from the IOMMU such as:DMAR: DRHD: handling fault status reg 202
DMAR: [DMA Write] Request device [00:04.0] fault addr
381fc0340000 [fault reason 05] PTE Write access is not setThis is because ntb_transport does not map the BAR space with the IOMMU.
To fix this, we map the entire MW region for each QP after we assign
the DMA channel. This prevents needing an extra DMA map in the fast
path.Link: https://lore.kernel.org/linux-pci/499934e7-3734-1aee-37dd-b42a5d2a2608@intel.com/
Signed-off-by: Logan Gunthorpe
Reviewed-by: Dave Jiang
Signed-off-by: Jon Mason -
If NTB peer host crashes or reboots, the NTB transport link will be
down and the MWs of NTB transport will be invalid. But the
ntb_transport_link_cleanup() does not free these invalid MWs. When
the NTB peer host is recovered later, NTB transport link will be
up and the ntb_set_mw() will not reset up MWs. Because the MWs of
NTB transport are invalid, the NTB transport will not work.We can fix it by freeing MWs when NTB transport link is down, then
the ntb_set_mw() will reset up MWs when NTB transport link is up.Signed-off-by: Joey Zhang
Reviewed-by: Logan Gunthorpe
Signed-off-by: Jon Mason -
Current Switchtec's BAR setup registers are limited to 32bits,
corresponding to the maximum MW (memory window) size is
Signed-off-by: Paul Selles
Signed-off-by: Wesley Sheng
Reviewed-by: Logan Gunthorpe
Signed-off-by: Jon Mason -
Switchtec NTB crosslink BARs are 64bit addressed but they are printed as
32bit addressed BARs. Fix debug log to increment the BAR numbers by 2 to
reflect the 64bit address alignment.Fixes: 017525018202 ("ntb_hw_switchtec: Add initialization code for crosslink")
Signed-off-by: Paul Selles
Signed-off-by: Wesley Sheng
Reviewed-by: Logan Gunthorpe
Signed-off-by: Jon Mason
28 Jan, 2019
1 commit
-
We need the char-misc fixes in here as well.
Signed-off-by: Greg Kroah-Hartman
22 Jan, 2019
2 commits
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Clean up the ifdefs which conditionally defined the io{read|write}64
functions in favour of the new common io-64-nonatomic-lo-hi header.Per a nit from Andy Shevchenko, the include list is also made
alphabetical.Signed-off-by: Logan Gunthorpe
Reviewed-by: Andy Shevchenko
Cc: Jon Mason
Signed-off-by: Greg Kroah-Hartman -
Now that ioread64 and iowrite64 are available in io-64-nonatomic,
we can remove the hack at the top of ntb_hw_intel.c and replace it
with an include.Signed-off-by: Logan Gunthorpe
Reviewed-by: Andy Shevchenko
Acked-by: Dave Jiang
Acked-by: Allen Hubbe
Acked-by: Jon Mason
Signed-off-by: Greg Kroah-Hartman
08 Jan, 2019
1 commit
-
We already need to zero out memory for dma_alloc_coherent(), as such
using dma_zalloc_coherent() is superflous. Phase it out.This change was generated with the following Coccinelle SmPL patch:
@ replace_dma_zalloc_coherent @
expression dev, size, data, handle, flags;
@@-dma_zalloc_coherent(dev, size, handle, flags)
+dma_alloc_coherent(dev, size, handle, flags)Suggested-by: Christoph Hellwig
Signed-off-by: Luis Chamberlain
[hch: re-ran the script on the latest tree]
Signed-off-by: Christoph Hellwig
01 Nov, 2018
4 commits
-
Since IDT PCIe-switch temperature sensor is now always available
irregardless of the EEPROM/BIOS settings, Kconfig and in-code
description should be properly altered. In addition lets update
the driver copyright lines.Signed-off-by: Serge Semin
Signed-off-by: Jon Mason -
IDT PCIe-switch temperature sensor interface is very broken. First
of all only a few combinations of TMPCTL threshold enable bits
really cause the interrupts unmasked. Even if an individual bit
indicates the event unmasked, corresponding IRQ just isn't generated.
Most of the threshold enable bits combinations are in fact useless and
non of them can help to create a fully functional alarm interface.
So to speak, we can't create a well defined hwmon alarms based on
the IDT PCI-switch threshold IRQs.Secondly a single threshold IRQ (not a combination of thresholds) can
be successfully enabled without the issue described above. But in this
case we experienced an enormous number of interrupts generated by
the chip if the temperature got near the enabled threshold value. Filter
adjustment didn't help much. It also doesn't provide a hysteresis settings.
Due to the temperature sample fluctuations near the threshold the
interrupts spate makes the system nearly unusable until the temperature
value finally settled so being pushed either to be fully higher or lower
the threshold.All of these issues makes the temperature sensor alarm interface useless
and even at some point dangerous to be used in the driver. In this case
it is safer to completely discard it and disable the temperature alarm
interrupts.Signed-off-by: Serge Semin
Signed-off-by: Jon Mason -
IDT PCIe switches provide an embedded temperature sensor working
within [0; 127.5]C with resolution of 0.5C. They also can generate
a PCIe upstream interrupt in case if the temperature passes through
specified thresholds. Since this thresholds interface is very broken
the created hwmon-sysfs interface exposes only the next set of hwmon
nodes: current input temperature, lowest and highest values measured,
history resetting, value offset. HWmon alarm interface isn't provided.IDT PCIe switch also've got an ADC/filter settings of the sensor.
This driver doesn't expose them to the hwmon-sysfs interface at the
moment, except the offset node.Signed-off-by: Serge Semin
Signed-off-by: Jon Mason -
In order to create a hwmon interface for the IDT PCIe-switch temperature
sensor the already available reader method should be improved. Particularly
we need to redesign it so one would be able to read temperature/offset
values from registers of the passed types. Since IDT sensor interface
provides temperature in unsigned format 0:7:1 (7 bits for real value
and one for fraction) we also need to have helpers for the typical sysfs
temperature data type conversion to and from this format. Even though
the IDT PCIe-switch provided temperature offset got the same but signed
type it can be translated by these methods too.Signed-off-by: Serge Semin
Signed-off-by: Jon Mason
