Eric Lee / smarc-fsl-linux-kernel

30 Dec, 2020

1 commit

  • 4771a82fa   soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe() ... Browse Code »

    [ Upstream commit c2867b2e710fc85bb39c6f6e5948450c48e8a33e ]

    Fix to return a negative error code from the error handling
    case instead of 0, as done elsewhere in this function.

    Fixes: e943c43b32ce ("PM: AVS: rockchip-io: Move the driver to the rockchip specific drivers")
    Reported-by: Hulk Robot
    Signed-off-by: Zhang Changzhong
    Link: https://lore.kernel.org/r/1607070805-33038-1-git-send-email-zhangchangzhong@huawei.com
    Signed-off-by: Heiko Stuebner
    Signed-off-by: Sasha Levin

    Zhang Changzhong
     

17 Oct, 2020

1 commit

  • e943c43b3   PM: AVS: rockchip-io: Move the driver to the rockchip specific drivers ... Browse Code »

    The avs drivers are all SoC specific drivers that doesn't share any code.
    Instead they are located in a directory, mostly to keep similar
    functionality together. From a maintenance point of view, it makes better
    sense to collect SoC specific drivers like these, into the SoC specific
    directories.

    Therefore, let's move the rockchip-io driver to the rockchip directory.

    Signed-off-by: Ulf Hansson
    Acked-by: Heiko Stuebner
    Signed-off-by: Rafael J. Wysocki

    Ulf Hansson
     

20 Jul, 2019

1 commit

  • 8362fd64f   Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc ... Browse Code »

    Pull ARM SoC-related driver updates from Olof Johansson:
    "Various driver updates for platforms and a couple of the small driver
    subsystems we merge through our tree:

    - A driver for SCU (system control) on NXP i.MX8QXP

    - Qualcomm Always-on Subsystem messaging driver (AOSS QMP)

    - Qualcomm PM support for MSM8998

    - Support for a newer version of DRAM PHY driver for Broadcom (DPFE)

    - Reset controller support for Bitmain BM1880

    - TI SCI (System Control Interface) support for CPU control on AM654
    processors

    - More TI sysc refactoring and rework"

    * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
    reset: remove redundant null check on pointer dev
    soc: rockchip: work around clang warning
    dt-bindings: reset: imx7: Fix the spelling of 'indices'
    soc: imx: Add i.MX8MN SoC driver support
    soc: aspeed: lpc-ctrl: Fix probe error handling
    soc: qcom: geni: Add support for ACPI
    firmware: ti_sci: Fix gcc unused-but-set-variable warning
    firmware: ti_sci: Use the correct style for SPDX License Identifier
    soc: imx8: Use existing of_root directly
    soc: imx8: Fix potential kernel dump in error path
    firmware/psci: psci_checker: Park kthreads before stopping them
    memory: move jedec_ddr.h from include/memory to drivers/memory/
    memory: move jedec_ddr_data.c from lib/ to drivers/memory/
    MAINTAINERS: Remove myself as qcom maintainer
    soc: aspeed: lpc-ctrl: make parameter optional
    soc: qcom: apr: Don't use reg for domain id
    soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
    memory: tegra: Fix -Wunused-const-variable
    firmware: tegra: Early resume BPMP
    soc/tegra: Select pinctrl for Tegra194
    ...

    Linus Torvalds
     

04 Jul, 2019

1 commit

  • b27aca2e5   soc: rockchip: work around clang warning ... Browse Code »

    clang emits a warning about a negative shift count for an
    unused part of a conditional constant expression:

    drivers/soc/rockchip/pm_domains.c:795:21: error: shift count is negative [-Werror,-Wshift-count-negative]
    [RK3328_PD_VIO] = DOMAIN_RK3328(-1, 8, 8, false),
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    drivers/soc/rockchip/pm_domains.c:129:2: note: expanded from macro 'DOMAIN_RK3328'
    DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    drivers/soc/rockchip/pm_domains.c:105:33: note: expanded from macro 'DOMAIN_M'
    .status_mask = (status >= 0) ? BIT(status) : 0, \
    ^~~~~~~~~~~
    include/linux/bits.h:6:24: note: expanded from macro 'BIT'

    This is a bug in clang that will be fixed in the future, but in order
    to build cleanly with clang-8, it would be helpful to shut up this
    warning. This file is the only instance reported by kernelci at the
    moment.

    The best solution I could come up with is to move the BIT() usage
    out of the macro into the instantiation, so we can avoid using
    BIT(-1).

    Link: https://lore.kernel.org/r/20190703153112.2767411-1-arnd@arndb.de
    Link: https://bugs.llvm.org/show_bug.cgi?id=38789
    Signed-off-by: Arnd Bergmann
    Reviewed-by: Nathan Chancellor
    Signed-off-by: Olof Johansson

    Arnd Bergmann
     

19 Jun, 2019

1 commit

  • d2912cb15   treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 ... Browse Code »

    Based on 2 normalized pattern(s):

    this program is free software you can redistribute it and or modify
    it under the terms of the gnu general public license version 2 as
    published by the free software foundation

    this program is free software you can redistribute it and or modify
    it under the terms of the gnu general public license version 2 as
    published by the free software foundation #

    extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

    has been chosen to replace the boilerplate/reference in 4122 file(s).

    Signed-off-by: Thomas Gleixner
    Reviewed-by: Enrico Weigelt
    Reviewed-by: Kate Stewart
    Reviewed-by: Allison Randal
    Cc: linux-spdx@vger.kernel.org
    Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
    Signed-off-by: Greg Kroah-Hartman

    Thomas Gleixner
     

21 May, 2019

1 commit

11 Apr, 2019

1 commit

  • bbdc00a7d   soc: rockchip: Set the proper PWM for rk3288 ... Browse Code »

    The rk3288 SoC has two PWM implementations available, the "old"
    implementation and the "new" one. You can switch between the two of
    them by flipping a bit in the grf.

    The "old" implementation is the default at chip power up but isn't the
    one that's officially supposed to be used. ...and, in fact, the
    driver that gets selected in Linux using the rk3288 device tree only
    supports the "new" implementation.

    Long ago I tried to get a switch to the right IP block landed in the
    PWM driver (search for "rk3288: Switch to use the proper PWM IP") but
    that got rejected. In the mean time the grf has grown a full-fledged
    driver that already sets other random bits like this. That means we
    can now get the fix landed.

    For those wondering how things could have possibly worked for the last
    4.5 years, folks have mostly been relying on the bootloader to set
    this bit. ...but occasionally folks have pointed back to my old patch
    series [1] in downstream kernels.

    [1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1391597.html

    Signed-off-by: Douglas Anderson
    Signed-off-by: Heiko Stuebner

    Douglas Anderson
     

06 Nov, 2018

1 commit

05 Nov, 2018

1 commit

05 Oct, 2018

1 commit

  • dc37a2525   soc: Convert to using %pOFn instead of device_node.name ... Browse Code »

    In preparation to remove the node name pointer from struct device_node,
    convert printf users to use the %pOFn format specifier.

    Cc: Li Yang
    Cc: David Brown
    Cc: Jonathan Hunter
    Cc: Santosh Shilimkar
    Cc: linuxppc-dev@lists.ozlabs.org
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-soc@vger.kernel.org
    Acked-by: Thierry Reding
    Acked-by: Heiko Stuebner
    Acked-by: Qiang Zhao
    Acked-by: Andy Gross
    Signed-off-by: Rob Herring

    Rob Herring
     

12 Jun, 2018

1 commit

  • 32bcbf8b6   Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ... Browse Code »

    Pull ARM SoC driver updates from Olof Johansson:
    "This contains platform-related driver updates for ARM and ARM64.

    Highlights:

    - ARM SCMI (System Control & Management Interface) driver cleanups

    - Hisilicon support for LPC bus w/ ACPI

    - Reset driver updates for several platforms: Uniphier,

    - Rockchip power domain bindings and hardware descriptions for
    several SoCs.

    - Tegra memory controller reset improvements"

    * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (59 commits)
    ARM: tegra: fix compile-testing PCI host driver
    soc: rockchip: power-domain: add power domain support for px30
    dt-bindings: power: add binding for px30 power domains
    dt-bindings: power: add PX30 SoCs header for power-domain
    soc: rockchip: power-domain: add power domain support for rk3228
    dt-bindings: power: add binding for rk3228 power domains
    dt-bindings: power: add RK3228 SoCs header for power-domain
    soc: rockchip: power-domain: add power domain support for rk3128
    dt-bindings: power: add binding for rk3128 power domains
    dt-bindings: power: add RK3128 SoCs header for power-domain
    soc: rockchip: power-domain: add power domain support for rk3036
    dt-bindings: power: add binding for rk3036 power domains
    dt-bindings: power: add RK3036 SoCs header for power-domain
    dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions
    memory: tegra: Remove Tegra114 SATA and AFI reset definitions
    memory: tegra: Register SMMU after MC driver became ready
    soc: mediatek: remove unneeded semicolon
    soc: mediatek: add a fixed wait for SRAM stable
    soc: mediatek: introduce a CAPS flag for scp_domain_data
    soc: mediatek: reuse regmap_read_poll_timeout helpers
    ...

    Linus Torvalds
     

10 Jun, 2018

1 commit

  • 6419945e3   Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux ... Browse Code »

    Pull clk updates from Stephen Boyd:
    "This time we have a good set of changes to the core framework that do
    some general cleanups, but nothing too major. The majority of the diff
    goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is
    introduced for Actions Semi so it takes up some lines to add all the
    different types, and the Qualcomm diff is there because we add support
    for two SoCs and it's quite a bit of data.

    Otherwise the big driver updates are on TI Davinci and Amlogic
    platforms. And then the long tail of driver updates for various fixes
    and stuff follows after that.

    Core:
    - debugfs cleanups removing error checking and an unused provider API
    - Removal of a clk init typedef that isn't used
    - Usage of match_string() to simplify parent string name matching
    - OF clk helpers moved to their own file (linux/of_clk.h)
    - Make clk warnings more readable across kernel versions

    New Drivers:
    - Qualcomm SDM845 GCC and Video clk controllers
    - Qualcomm MSM8998 GCC
    - Actions Semi S900 SoC support
    - Nuvoton npcm750 microcontroller clks
    - Amlogic axg AO clock controller

    Removed Drivers:
    - Deprecated Rockchip clk-gate driver

    Updates:
    - debugfs functions stopped checking return values
    - Support for the MSIOF module clocks on Rensas R-Car M3-N
    - Support for the new Rensas RZ/G1C and R-Car E3 SoCs
    - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs
    - Berlin and Amlogic SPDX tagging
    - Usage of of_clk_get_parent_count() in more places
    - Proper implementation of the CDEV1/2 clocks on Tegra20
    - Allwinner H6 PRCM clock support and R40 EMAC support
    - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet
    - Round closest support for meson's mpll driver
    - Support for meson8b nand clocks and gxbb video decoder clocks
    - Mediatek mali clks
    - STM32MP1 fixes
    - Uniphier LD11/LD20 stream demux system clock"

    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
    clk: qcom: Export clk_fabia_pll_configure()
    clk: bcm: Update and add Stingray clock entries
    dt-bindings: clk: Update Stingray binding doc
    clk-si544: Properly round requested frequency to nearest match
    clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
    clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
    clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
    clk: ingenic: jz4770: Change OTG from custom to standard gated clock
    clk: ingenic: Support specifying "wait for clock stable" delay
    clk: ingenic: Add support for clocks whose gate bit is inverted
    clk: use match_string() helper
    clk: bcm2835: use match_string() helper
    clk: Return void from debug_init op
    clk: remove clk_debugfs_add_file()
    clk: tegra: no need to check return value of debugfs_create functions
    clk: davinci: no need to check return value of debugfs_create functions
    clk: bcm2835: no need to check return value of debugfs_create functions
    clk: no need to check return value of debugfs_create functions
    clk: imx6: add EPIT clock support
    clk: mvebu: use correct bit for 98DX3236 NAND
    ...

    Linus Torvalds
     

07 Jun, 2018

1 commit

  • 0ed2dd03b   treewide: Use struct_size() for devm_kmalloc() and friends ... Browse Code »

    Replaces open-coded struct size calculations with struct_size() for
    devm_*, f2fs_*, and sock_* allocations. Automatically generated (and
    manually adjusted) from the following Coccinelle script:

    // Direct reference to struct field.
    @@
    identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
    expression HANDLE;
    expression GFP;
    identifier VAR, ELEMENT;
    expression COUNT;
    @@

    - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP)
    + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)

    // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
    @@
    identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
    expression HANDLE;
    expression GFP;
    identifier VAR, ELEMENT;
    expression COUNT;
    @@

    - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP)
    + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)

    // Same pattern, but can't trivially locate the trailing element name,
    // or variable name.
    @@
    identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
    expression HANDLE;
    expression GFP;
    expression SOMETHING, COUNT, ELEMENT;
    @@

    - alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP)
    + alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP)

    Signed-off-by: Kees Cook

    Kees Cook
     

24 May, 2018

4 commits

14 May, 2018

1 commit

02 May, 2018

1 commit

06 Mar, 2018

3 commits

12 Feb, 2018

1 commit

08 Nov, 2017

1 commit

21 Jul, 2017

1 commit

16 Jul, 2017

1 commit

06 Jan, 2017

1 commit

  • 4c58063d4   soc: rockchip: add driver handling grf setup ... Browse Code »

    The General Register Files are an area of registers containing a lot
    of single-bit settings for numerous components as well full components
    like usbphy control. Therefore all used components are accessed
    via the syscon provided by the grf nodes or from the sub-devices
    created through the simple-mfd created from the grf node.

    Some settings are not used by anything but will need to be set up
    according to expectations on the kernel side.

    Best example is the force_jtag setting, which defaults to on and
    results in the soc switching the pin-outputs between jtag and sdmmc
    automatically depending on the card-detect status. This conflicts
    heavily with how the dw_mmc driver expects to do its work and also
    with the clock-controller, which has most likely deactivated the
    jtag clock due to it being unused.

    So far the handling of this setting was living in the mach-rockchip
    code for the arm32-based rk3288 but that of course doesn't work
    for arm64 socs and would also look ugly for further arm32 socs.

    Also always disabling this setting is quite specific to linux and
    its subsystems, other operating systems might prefer other settings,
    so that the bootloader cannot really set a sane default for all.

    So introduce a top-level driver for the grf that handles these
    settings that need to be a certain way but nobody cares about.

    Other needed settings might surface in the future and can then
    be added here, but only as a last option. Ideally general GRF
    settings should be handled in the driver needing them.

    Signed-off-by: Heiko Stuebner
    Reviewed-by: Douglas Anderson

    Heiko Stuebner
     

05 Jan, 2017

2 commits

11 Nov, 2016

2 commits

02 Nov, 2016

1 commit

  • e4c8cd82d   soc: rockchip: power-domain: avoid infinite loop ... Browse Code »

    In some cases, we have met the infinite loop in
    rockchip_pmu_set_idle_request() or rockchip_do_pmu_set_power_domain().

    As the crosbug.com/p/57351 reported, the boot hangs right after this
    [1.629163] bootconsole [uart8250] disabled
    [1.639286] [drm:drm_core_init] Initialized drm 1.1.0 20060810
    [1.645926] [drm:drm_get_platform_dev] Initialized vgem 1.0.0 20120112..
    [1.654558] iommu: Adding device ff8f0000.vop to group 0
    [1.660569] iommu: Adding device ff900000.vop to group 1

    This patch adds the error message and timeout to avoid infinite loop if
    it fails to get the ack.

    Signed-off-by: Caesar Wang
    Signed-off-by: Heiko Stuebner

    Caesar Wang
     

16 Oct, 2016

1 commit

  • 3f2fe461c   soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts ... Browse Code »

    On rk3288 it was important that powerdown and powerup counts for the
    CPU/GPU in the kernel because:
    * The power on default was crazy long.
    * We couldn't rely on the firmware to set this up because really this
    wasn't the firmware's job--the kernel was the only one that really
    cared about bringing up / down CPUs and the GPU and doing suspend /
    resume (which involves bringing up / down CPUs).

    On newer ARM systems (like rk3399) ARM Trusted Firmware is in charge of
    bringing up and down the CPUs and it really should be in charge of
    setting all these counts right. After all ATF is in charge of suspend /
    resume and CPU up / down. Let's get out of the way and let ATF do its
    job.

    A few other motivations for doing this:
    * Depending on another configuration (PMU_24M_EN_CFG) these counts can
    be either in 24M or 32k cycles. Thus, though ATF isn't really so
    involved in bringing up the GPU, ATF should probably manage the counts
    for everything so it can also manage the 24M / 32k choice.
    * It turns out that (right now) 24M mode is broken on rk3399 and not
    being used. That means that the count the kernel was programming
    in (24) was not 1 us (which it seems was intended) but was actually
    .75 ms
    * On rk3399 there are actually 2 separate registers for setting CPU
    up/down time plus 1 register for GPU up/down time. The curent kernel
    code actually was putting the register for the "little" cores in the
    "CPU" slot and the register for the "big" cores in the "GPU" slot. It
    was never initting the GPU counts.

    Note: this change assumes that ATF will actually set these values at
    boot, as I'm proposing in .

    Signed-off-by: Douglas Anderson
    [ATF change has landed]
    Signed-off-by: Heiko Stuebner

    Douglas Anderson
     

19 Aug, 2016

1 commit

22 Apr, 2016

1 commit

12 Apr, 2016

1 commit

28 Mar, 2016

4 commits