18 Jun, 2009
8 commits
-
ia64 was assigning resources to root busses after allocations had
been made for child busses. Calling pcibios_setup_root_windows() from
pcibios_fixup_bus() solves this problem by assigning the resources to
the root bus before child busses are scanned.Signed-off-by: Matthew Wilcox
Tested-by: Andrew Patterson
Signed-off-by: Linus Torvalds -
Instead of open-coding pci_find_parent_resource and request_resource,
just call pci_claim_resource.Signed-off-by: Matthew Wilcox
Signed-off-by: Linus Torvalds -
This function was only used by pci_claim_resource(), and the last commit
deleted that use.Signed-off-by: Matthew Wilcox
Signed-off-by: Linus Torvalds -
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
[IA64] Convert ia64 to use int-ll64.h
[IA64] Fix build error in paravirt_patchlist.c
[IA64] ia64 does not need umount2() syscall
[IA64] hook up new rt_tgsigqueueinfo syscall
[IA64] msi_ia64.c dmar_msi_type should be static
[IA64] remove obsolete hw_interrupt_type
[IA64] remove obsolete irq_desc_t typedef
[IA64] remove obsolete no_irq_type
[IA64] unexport fpswa.h -
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq:
[CPUFREQ] cpumask: new cpumask operators for arch/x86/kernel/cpu/cpufreq/powernow-k8.c
[CPUFREQ] cpumask: avoid playing with cpus_allowed in powernow-k8.c
[CPUFREQ] cpumask: avoid cpumask games in arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
[CPUFREQ] cpumask: avoid playing with cpus_allowed in speedstep-ich.c
[CPUFREQ] powernow-k8: get drv data for correct CPU
[CPUFREQ] powernow-k8: read P-state from HW
[CPUFREQ] reduce scope of ACPI_PSS_BIOS_BUG_MSG[]
[CPUFREQ] Clean up convoluted code in arch/x86/kernel/tsc.c:time_cpufreq_notifier()
[CPUFREQ] minor correction to cpu-freq documentation
[CPUFREQ] powernow-k8.c: mess cleanup
[CPUFREQ] Only set sampling_rate_max deprecated, sampling_rate_min is useful
[CPUFREQ] powernow-k8: Set transition latency to 1 if ACPI tables export 0
[CPUFREQ] ondemand: Uncouple minimal sampling rate from HZ in NO_HZ case -
It is generally agreed that it would be beneficial for u64 to be an
unsigned long long on all architectures. ia64 (in common with several
other 64-bit architectures) currently uses unsigned long. Migrating
piecemeal is too painful; this giant patch fixes all compilation warnings
and errors that come as a result of switching to use int-ll64.h.Note that userspace will still see __u64 defined as unsigned long. This
is important as it affects C++ name mangling.[Updated by Tony Luck to change efi.h:efi_freemem_callback_t to use
u64 for start/end rather than unsigned long]Signed-off-by: Matthew Wilcox
Signed-off-by: Tony Luck -
Andrew cleaned up some #include tangles in:
commit 0d9c25dde878a636ee9a9b53923569171bf9a55b
headers: move module_bug_finalize()/module_bug_cleanup() definitions into module.hwhich resulted in this build error for ia64:
CC arch/ia64/kernel/paravirt_patchlist.o
arch/ia64/kernel/paravirt_patchlist.c:43: error: expected '=', ',', ';', 'asm' or '__attribute__' before '__initdata'
arch/ia64/kernel/paravirt_patchlist.c:54: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'paravirt_get_gate_patchlist'
arch/ia64/kernel/paravirt_patchlist.c:76: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'paravirt_get_gate_section'
make[1]: *** [arch/ia64/kernel/paravirt_patchlist.o] Error 1The problem was that paravirt_patchlist.c was relying on some of the
nested includes (specifically that linux/bug.h included linux/module.hSigned-off-by: Jes Sorensen
Signed-off-by: Tony Luck
17 Jun, 2009
32 commits
-
[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
support. As implemented in this patch cache and tlb flushing will also be
invoked with interrupts disabled so smp_call_function() will blow up in
charming ways. So limit to !SMP.]Reviewed-by: Pavel Machek
Reviewed-by: Yan Hua
Reviewed-by: Arnaud Patard
Reviewed-by: Atsushi Nemoto
Signed-off-by: Wu Zhangjin
Signed-off-by: Hu Hongbing
Signed-off-by: Ralf Baechle -
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.hSigned-off-by: David Daney
Signed-off-by: Ralf Baechle -
Some CPUs have implementation dependent rdhwr registers. Allow them
to be enabled on a per CPU basis.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Add new kconfig variables SYS_SUPPORTS_HUGETLBFS and
CPU_SUPPORTS_HUGEPAGES. They are enabled for systems that are known
to support huge pages.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
The TLB handlers need to check for huge pages and give them special
handling. Huge pages consist of two contiguous sub-pages of physical
memory.* Loading entrylo0 and entrylo1 need to be handled specially.
* The page mask must be set for huge pages and then restored after
writing the TLB entries.* The PTE for huge pages resides in the PMD, we halt traversal of the
tables there.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
The l parameter to iPTE_LW() is unused. Remove it and from some of its
callers as well.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
The octeon-ethernet driver needs to check for additional chip specific
features, we add them to the octeon_has_feature() framework.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
The bootloader now uses additional board type constants. The
octeon-ethernet driver needs some of the new values.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
The various Octeon ethernet drivers use these new functions.
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Replace a few open-coded GPIO register accesses with gpio calls.
Signed-off-by: Manuel Lauss
Signed-off-by: Ralf Baechle -
Replace a few GPIO register accesses in the board init code with calls to
the gpio api.Signed-off-by: Manuel Lauss
Signed-off-by: Ralf Baechle -
Replace a few GPIO register accesses in the board init code with calls
to the gpio api.Signed-off-by: Manuel Lauss
Signed-off-by: Ralf Baechle -
The current in-kernel Alchemy GPIO support is far too inflexible for
all my use cases. To address this, the following changes are made:* create generic functions which deal with manipulating the on-chip
GPIO1/2 blocks. Such functions are universally useful.
* Macros for GPIO2 shared interrupt management and block control.
* support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros.If CONFIG_GPIOLIB is not enabled, provide linux gpio framework
compatibility by directly inlining the GPIO1/2 functions. GPIO access
is limited to on-chip ones and they can be accessed as documented in
the datasheets (GPIO0-31 and 200-215).If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and
one for GPIO2, are registered. GPIOs can still be accessed by using
the numberspace established in the databooks.However this is not yet flexible enough for my uses: My Alchemy
systems have a documented "external" gpio interface (fixed, different
numberspace) and can support a variety of baseboards, some of which
are equipped with I2C gpio expanders. I want to be able to provide
the default 16 GPIOs of the CPU board numbered as 0..15 and also
support gpio expanders, if present, starting as gpio16.To achieve this, a new Kconfig symbol for Alchemy is introduced,
CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal
that they don't want the Alchemy numberspace exposed to the outside
world, but instead want to provide their own. Boards are now respon-
sible for providing the linux gpio interface glue code (either in a
custom gpio.h header (in board include directory) or with gpio_chips).To make the board-specific inlined gpio functions work, the MIPS
Makefile must be changed so that the mach-au1x00/gpio.h header is
included _after_ the board headers, by moving the inclusion of
the mach-au1x00/ to the end of the header list.See arch/mips/include/asm/mach-au1x00/gpio.h for more info.
Signed-off-by: Manuel Lauss
Acked-by: Florian Fainelli
Signed-off-by: Ralf Baechle -
Signed-off-by: Manuel Lauss
Signed-off-by: Ralf Baechle -
gpio_direction_output should also set an output value according to the API.
Signed-off-by: Matthieu CASTET
Acked-by: Aurelien Jarno
Signed-off-by: Ralf Baechle -
o Rewrite to use . Cuts down the file from 40 to
16 lines.
o Delete _IOC_VOID, _IOC_OUT, _IOC_IN and _IOC_INOUT. They were added
for 2.1.14 but I was not able to find any user - not even historical
ones.Signed-off-by: Ralf Baechle
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Add platform support for RNG of TX4939 SoC.
Signed-off-by: Atsushi Nemoto
Signed-off-by: Ralf Baechle -
Add a sysdev to access SRAM in TXx9 SoCs via sysfs.
Signed-off-by: Atsushi Nemoto
Signed-off-by: Ralf Baechle -
CFE is the only supported and used bootloader on the SiByte boards,
the standalone kernel support has been never used outside Broadcom.
Remove it and make the kernel use CFE by default.Signed-off-by: Imre Kaloz
Signed-off-by: Ralf Baechle -
This patch removes the SiByte simulation Kconfig option, which only modified
a printk.Signed-off-by: Imre Kaloz
Signed-off-by: Ralf Baechle -
This patch makes sure that we are not going to clear
or change the interrupt status of a GPIO interrupt
superior to 13 as this is the maximum number of GPIO
interrupt source (p.232 of the RC32434 reference manual).Signed-off-by: Florian Fainelli
Signed-off-by: Ralf Baechle -
Remove commented out definitions.
Signed-off-by: Florian Fainelli
Signed-off-by: Ralf Baechle -
CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch. This
label in the switch statement is dead code, so we remove it.Signed-off-by: David Daney
Reviewed by: David VomLehn
Signed-off-by: Ralf Baechle -
The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.Signed-off-by: David Daney
Reviewed by: David VomLehn
Signed-off-by: Ralf Baechle -
Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Try to fold the 64-bit TLB refill handler opportunistically at the
beginning of the vmalloc path so as to avoid splitting execution flow in
half and wasting cycles for a branch required at that point then. Resort
to doing the split if either of the newly created parts would not fit into
its designated slot.Original-patch-by: Maciej W. Rozycki
Signed-off-by: Maciej W. Rozycki
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
The logic used to split the r4000 refill handler is liberally
sprinkled with magic numbers. We attempt to explain what they are and
normalize them against a new symbolic value (MIPS64_REFILL_INSNS).CC: David VomLehn
Reviewed-by: Paul Gortmaker
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle -
Add platform support for ACLC of TXx9 SoCs.
Signed-off-by: Atsushi Nemoto
Acked-by: Mark Brown
Signed-off-by: Ralf Baechle
