10 Jan, 2017
1 commit
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The CDCE925 is a member of the CDCE(L)9xx programmable clock generator
family. There are also CDCE913, CDCE937, CDCE949 which have different
number of PLLs and outputs.The clk-cdce925 driver supports only CDCE925 in the family. This adds
support for the CDCE913, CDCE937, CDCE949, too.Signed-off-by: Akinobu Mita
Acked-by: Rob Herring
Cc: Mike Looijmans
Cc: Michael Turquette
Cc: Stephen Boyd
Signed-off-by: Stephen Boyd
09 Dec, 2016
1 commit
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It is likely that instead of '1>64', 'q>64' was expected.
Moreover, according to datasheet,
http://www.ti.com/lit/ds/symlink/cdce925.pdf
SCAS847I - JULY 2007 - REVISED OCTOBER 2016
PLL settings limits are: 16
Signed-off-by: Stephen Boyd
25 Aug, 2016
1 commit
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Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.Cc: Mike Looijmans
Signed-off-by: Stephen Boyd
Signed-off-by: Stephen Boyd
21 Jul, 2015
1 commit
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This clock provider uses the consumer API, so include clk.h
explicitly.Cc: Mike Looijmans
Signed-off-by: Stephen Boyd
11 Jun, 2015
1 commit
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drivers/clk/clk-cdce925.c:550: warning: format ‘%u’ expects type
‘unsigned int’, but argument 6 has type ‘size_t’Cc: Mike Looijmans
Reported-by: kbuild test robot
Signed-off-by: Stephen Boyd
04 Jun, 2015
1 commit
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This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.Signed-off-by: Mike Looijmans
Signed-off-by: Michael Turquette
